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dc.contributor.authorPérez Puigdemont, Jordi
dc.contributor.authorCalomarde Palomino, Antonio
dc.contributor.authorMoll Echeto, Francisco de Borja
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria de Sistemes, Automàtica i Informàtica Industrial
dc.date.accessioned2015-03-20T14:48:12Z
dc.date.available2015-03-20T14:48:12Z
dc.date.created2014
dc.date.issued2014
dc.identifier.citationPerez, J.; Calomarde, A.; Moll, F. All-digital self-adaptive PVTA variation aware clock generation system for DFS. A: European Workshop on CMOS Variability. "Proceedings of the 5th European Workshop on CMOS Variability". Palma de Mallorca: 2014, p. 1-4.
dc.identifier.isbn978-147995399-8
dc.identifier.urihttp://hdl.handle.net/2117/26905
dc.description.abstractAn all-digital self-adaptive clock generation system capable of adapt the clock frequency to compensate the effects of PVTA variations on the IC propagation delay and satisfy an externally set propagation length condition is presented. The design uses time-to-digital converters (TDCs) to measure the propagation length and a variable length ring oscillator (VLRO) to synthesize the clock signal. The VLRO naturally adapts its frequency to the PVTA variations suffered by its logic gates while the TDCs are used to track these variations across the chip and modify the VLRO length in order to adapt the clock frequency to them. The system measurements, for a 45nm FPGA, show that it adapts the VLRO length, and therefore the clock frequency, to satisfy the propagation length condition. Measurements also prove the system capabilities to act as a dynamic frequency scaling clock source since the propagation length condition value act as a frequency selection input and a strong linear relation between the input value and the resultant clock period is present.
dc.format.extent4 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subject.lcshTransistors
dc.subject.otherClock generation system
dc.subject.otherFrequency selection
dc.subject.otherPropagation delays
dc.subject.otherPropagation lengths
dc.subject.otherSystem capabilities
dc.subject.otherSystem measurement
dc.subject.otherTime to digital converters (TDCs)
dc.subject.otherVariable length
dc.titleAll-digital self-adaptive PVTA variation aware clock generation system for DFS
dc.typeConference report
dc.subject.lemacTransistors
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/VARI.2014.6957084
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
drac.iddocument15415399
dc.description.versionPostprint (author’s final draft)
upcommons.citation.authorPerez, J.; Calomarde, A.; Moll, F.
upcommons.citation.contributorEuropean Workshop on CMOS Variability
upcommons.citation.pubplacePalma de Mallorca
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings of the 5th European Workshop on CMOS Variability
upcommons.citation.startingPage1
upcommons.citation.endingPage4


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