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dc.contributor.authorNeagu, Madalin
dc.contributor.authorMiclea, Liviu
dc.contributor.authorManich Bou, Salvador
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2015-03-19T10:48:23Z
dc.date.available2015-03-19T10:48:23Z
dc.date.created2015
dc.date.issued2015
dc.identifier.citationNeagu, M.; Miclea, L.; Manich, S. On the use of error detecting and correcting codes to boost security in caches against side channel attacks. A: Workshop on Trustworthy Manufacturing and Utilization of Secure Devices. "Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition: 9-13 March 2015, Grenoble, France". Grenoble: 2015, p. 1-6.
dc.identifier.isbn978-3-9815370-4-8
dc.identifier.urihttp://hdl.handle.net/2117/26828
dc.description.abstractMicroprocessor memory is sensitive to cold boot attacks. In this kind of attacks, memory remanence is exploited to download its content after the microprocessor has been struck by a hard boot. If just in this moment, a crypto-algorithm was in execution, the memory data can be downloaded into a backup memory and specialized tools can be used to extract the secret keys. In the main memory data can be protected using efficient encryption techniques but in caches this is not possible unless the performance becomes seriously degraded. Recently, an interleaved scrambling technique (IST) was presented to improve the security of caches against cold boot attacks. While IST is effective for this particular kind of attacks, a weakness exists against side channel attacks, in particular using power analysis. Reliability of data in caches is warranted by means of error detecting and correcting codes. In this work it is shown how these kinds of codes can be used not only to improve reliability but also the security of data. In particular, a self-healing technique is selected to make the IST technique robust against side channel attacks using power analysis.
dc.format.extent6 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Seguretat informàtica
dc.subject.lcshDigital signatures
dc.subject.lcshCryptography
dc.subject.lcshCache memory
dc.subject.otherdata scrambling
dc.subject.othercache memories
dc.subject.othercold boot attack
dc.subject.otherself-healing memories
dc.subject.otherside channel attack
dc.titleOn the use of error detecting and correcting codes to boost security in caches against side channel attacks
dc.typeConference report
dc.subject.lemacXifratge (Informàtica)
dc.subject.lemacCriptografia
dc.subject.lemacMemòria ràpida de treball (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.relation.publisherversionhttp://www.date-conference.com/conference/workshop-w10
dc.rights.accessOpen Access
drac.iddocument15520126
dc.description.versionPostprint (author’s final draft)
upcommons.citation.authorNeagu, M.; Miclea, L.; Manich, S.
upcommons.citation.contributorWorkshop on Trustworthy Manufacturing and Utilization of Secure Devices
upcommons.citation.pubplaceGrenoble
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition: 9-13 March 2015, Grenoble, France
upcommons.citation.startingPage1
upcommons.citation.endingPage6


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