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dc.contributor.authorFransi Palos, Sergi
dc.contributor.authorFarre Lozano, Goretti
dc.contributor.authorGarcia Deiros, Lucas
dc.contributor.authorManich Bou, Salvador
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2015-03-18T08:50:30Z
dc.date.created2010-05-24
dc.date.issued2010-05-24
dc.identifier.citationFransi, S. [et al.]. Design and implementation of automatic test equipment IP module. A: IEEE European Test Symposium. "15th IEEE European Test Symposium: 24-28 May 2010: ETS 2010, Praga : digest of papers". Praga: Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 244.
dc.identifier.isbn978-1-4244-5833-2
dc.identifier.urihttp://hdl.handle.net/2117/26780
dc.description.abstractThis paper presents an Intellectual Property (IP) module that includes fully functional autonomous Automatic Test Equipment (ATE). The module analyses responses from the Device Under Test (DUT) after sending test vectors to the device. Communication with the DUT is maintained through a synchronous bidirectional serial channel. The module has been designed for a fail-safe level of security, which means any single fault producing an erroneous output is detected. Several IP-ATEs can be synthesized in a single hardware platform to operate independently or coordinately.
dc.format.extent1 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshDigital integrated circuits -- Testing
dc.subject.otherAutomatic Testing
dc.subject.otherDigital Circuits
dc.subject.otherField Programmable Gate Arrays
dc.subject.otherIntellectual Property
dc.subject.otherLow Power Tester
dc.subject.otherLow Cost ICs
dc.subject.otherMultisite Tester.
dc.titleDesign and implementation of automatic test equipment IP module
dc.typeConference lecture
dc.subject.lemacCircuits integrats digitals -- Proves
dc.contributor.groupUniversitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat
dc.identifier.dlCFP10216-USB
dc.rights.accessRestricted access - publisher's policy
drac.iddocument2543199
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorFransi, S.; Farre, G.; Deiros, L. G.; Manich, S.
upcommons.citation.contributorIEEE European Test Symposium
upcommons.citation.pubplacePraga
upcommons.citation.publishedtrue
upcommons.citation.publicationName15th IEEE European Test Symposium: 24-28 May 2010: ETS 2010, Praga : digest of papers
upcommons.citation.startingPage244
upcommons.citation.endingPage244


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