TM-dietlibc: A TM-aware real-world system library
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés restringit per política de l'editorial
Projecte de la Comissió EuropeaHIPEAC - High Performance and Embedded Architecture and Compilation (EC-FP7-287759)
The simplicity of concurrent programming with Transactional Memory (TM) and its recent implementation in mainstream processors greatly motivates researchers and industry to investigate this field and propose new implementations and optimizations. However, there is still no standard C system library which a wide range of TM developers can adopt. TM application developers have been forced to avoid library calls inside of transactions or to execute them irrevocably (i.e. in serial order). In this paper, we present the first TM-aware system library, a complex software implementation integrated with TM principles and suited for software (STM), hardware (HTM) and hybrid TM (HyTM). The library we propose is derived from a modified lock-based implementation and can be used with the existing standard C API. In our work, we describe design challenges and code optimizations that would be specific to any TMbased system library or application. We argue about system call execution within transactions, highlighting the possibility of unexpected results from threads. For this reason we propose: (1) a mechanism for detecting conflicts over kernel data in user space, and (2) a new barrier to allow hybrid TM to be used effectively with system libraries. Our evaluation includes different TM implementations and the focus is on memory management and file operations since they are widely used in applications and require additional mechanisms for concurrent execution. We show the benefit we gain with our libc modifications providing parallel execution as much as possible. The library we propose shows high scalability when linked with STM and HTM. For file operations it shows on average a 1.1, 2.6 and 3.7x performance speedup for 8 cores using HyTM, STM and HTM, respectively (over a lock-based single-threaded execution). For a red-black tree it shows on average 3.14x performance speedup for 8 cores using STM (over a multi-read single-threaded execution).
CitacióSmiljkovic, V. [et al.]. TM-dietlibc: A TM-aware real-world system library. A: IEEE International Parallel and Distributed Processing Symposium. "IEEE 27th International Parallel and Distributed Processing Symposium: 20–24 May 2013, Boston, Massachusetts: proceedings". Boston, MA: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 1266-1274.
Versió de l'editorhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6569902