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dc.contributor.authorAlvanos, Michail
dc.contributor.authorAmaral, José Nelson
dc.contributor.authorTiotto, Ettore
dc.contributor.authorFarreras Esclusa, Montserrat
dc.contributor.authorMartorell Bofill, Xavier
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationAlvanos, M. [et al.]. Reducing compiler-inserted instrumentation in unified-parallel-C code generation. A: International Symposium on Computer Architecture and High Performance Computing. "IEEE 26th International Symposium on Computer Architecture and High Performance Computing: 22–24 October 2014: Paris, France: proceedings". París: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 270-277.
dc.description.abstractPrograms written in Partitioned Global Address Space (PGAS) languages can access any location of the entire address space via standard read/write operations. However, the compiler have to create the communication mechanisms and the runtime system to use synchronization primitives to ensure the correct execution of the programs. However, PGAS programs may have fine-grained shared accesses that lead to performance degradation. One solution is to use the inspector-executor technique to determine which accesses are indeed remote and which accesses may be coalesced in larger remote access operations. A straightforward implementation of the inspector-executor in a PGAS system may result in excessive instrumentation that hinders performance. This paper introduces a shared-data localization transformation based on linear memory descriptors (LMADs) that reduces the amount of instrumentation introduced by the compiler into programs written in the UPC language and describes a prototype implementation of the proposed transformation. A performance evaluation, using up to 2048 cores of a POWER 775 supercomputer, allows for a prediction that applications with regular accesses can achieve up to 180% of the performance of handoptimized versions while applications with irregular accesses yield performance gain from 1.12X up to 6.3X speedup.
dc.format.extent8 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subjectÀrees temàtiques de la UPC::Informàtica::Llenguatges de programació
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshProgramming languages (Electronic computers)
dc.subject.otherComputer architecture
dc.subject.otherLinear transformations
dc.subject.otherMathematical transformations
dc.subject.otherProgram compilers
dc.subject.otherSupercomputers Communication mechanisms
dc.subject.otherData localization
dc.subject.otherPartitioned Global Address Space
dc.subject.otherPerformance degradation
dc.subject.otherPrototype implementations
dc.subject.otherRead/write operations
dc.subject.otherSynchronization primitive
dc.subject.otherTransformation based
dc.titleReducing compiler-inserted instrumentation in unified-parallel-C code generation
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.subject.lemacLlenguatges de programació
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessRestricted access - publisher's policy
dc.description.versionPostprint (published version)
local.citation.authorAlvanos, M.; Amaral, J.N.; Tiotto, E.; Farreras, M.; Martorell, X.
local.citation.contributorInternational Symposium on Computer Architecture and High Performance Computing
local.citation.publicationNameIEEE 26th International Symposium on Computer Architecture and High Performance Computing: 22–24 October 2014: Paris, France: proceedings

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