Show simple item record

dc.contributor.authorTanasic, Ivan
dc.contributor.authorGelado Fernandez, Isaac
dc.contributor.authorCabezas, Javier
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorNavarro, Nacho
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2015-01-27T10:54:36Z
dc.date.available2015-01-27T10:54:36Z
dc.date.created2014
dc.date.issued2014
dc.identifier.citationTanasic, I. [et al.]. Enabling preemptive multiprogramming on GPUs. A: International Symposium on Computer Architecture. "ISCA 2014: the 41st Annual International Symposium on Computer Architecture: June 14-18, 2014: Minneapolis, MN, USA". Minneapolis: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 193-204.
dc.identifier.isbn978-147994396-8
dc.identifier.urihttp://hdl.handle.net/2117/26093
dc.description.abstractGPUs are being increasingly adopted as compute accelerators in many domains, spanning environments from mobile systems to cloud computing. These systems are usually running multiple applications, from one or several users. However GPUs do not provide the support for resource sharing traditionally expected in these scenarios. Thus, such systems are unable to provide key multiprogrammed workload requirements, such as responsiveness, fairness or quality of service. In this paper, we propose a set of hardware extensions that allow GPUs to efficiently support multiprogrammed GPU workloads. We argue for preemptive multitasking and design two preemption mechanisms that can be used to implement GPU scheduling policies. We extend the architecture to allow concurrent execution of GPU kernels from different user processes and implement a scheduling policy that dynamically distributes the GPU cores among concurrently running kernels, according to their priorities. We extend the NVIDIA GK110 (Kepler) like GPU architecture with our proposals and evaluate them on a set of multiprogrammed workloads with up to eight concurrent processes. Our proposals improve execution time of high-priority processes by 15.6x, the average application turnaround time between 1.5x to 2x, and system fairness up to 3.4x.
dc.description.sponsorshipWe would like to thank the anonymous reviewers, Alexan- der Veidenbaum, Carlos Villavieja, Lluis Vilanova, Lluc Al- varez, and Marc Jorda on their comments and help improving our work and this paper. This work is supported by Euro- pean Commission through TERAFLUX (FP7-249013), Mont- Blanc (FP7-288777), and RoMoL (GA-321253) projects, NVIDIA through the CUDA Center of Excellence program, Spanish Government through Programa Severo Ochoa (SEV-2011-0067) and Spanish Ministry of Science and Technology through TIN2007-60625 and TIN2012-34557 projects.
dc.format.extent12 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprogramming (Electronic computers)
dc.subject.lcshGraphics processing units
dc.subject.otherMultiprogramming
dc.subject.otherQuality of service
dc.subject.otherTurnaround time
dc.subject.otherConcurrent execution
dc.subject.otherConcurrent process
dc.subject.otherHardware extension
dc.subject.otherPreemptive multitasking
dc.subject.otherResource sharing
dc.subject.otherScheduling policies
dc.subject.otherSystem fairness
dc.subject.otherProgram processors
dc.titleEnabling preemptive multiprogramming on GPUs
dc.typeConference report
dc.subject.lemacMultiprogramació (Ordinadors electrònics)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/ISCA.2014.6853208
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6853208&queryText%3DEnabling+preemptive+multiprogramming+on+GPUs
dc.rights.accessOpen Access
local.identifier.drac15248335
dc.description.versionPostprint (author’s final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
local.citation.authorTanasic, I.; Gelado, I.; Cabezas, J.; Alex Ramirez; Navarro, N.; Valero, M.
local.citation.contributorInternational Symposium on Computer Architecture
local.citation.pubplaceMinneapolis
local.citation.publicationNameISCA 2014: the 41st Annual International Symposium on Computer Architecture: June 14-18, 2014: Minneapolis, MN, USA
local.citation.startingPage193
local.citation.endingPage204


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder