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Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design
dc.contributor.author | Pouyan, Peyman |
dc.contributor.author | Amat Bertran, Esteve |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2015-01-13T10:48:43Z |
dc.date.available | 2015-02-25T14:52:58Z |
dc.date.created | 2014 |
dc.date.issued | 2014 |
dc.identifier.citation | Pouyan, P.; Amat, Esteve; Rubio, A. Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design. "IEEE transactions on very large scale integration (VLSI) systems", 2014. |
dc.identifier.issn | 1063-8210 |
dc.identifier.uri | http://hdl.handle.net/2117/25262 |
dc.description.abstract | Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive reconfiguration is an emerging technique oriented to extend the system lifetime of memories affected by aging. In this brief, we present a new approach for static random access memory (SRAM) design that extends the cache lifetime when considering process variation and aging in the memory cells using an adaptive strategy. To track the aging in the SRAM cells we propose an on-chip monitoring technique. Our results show the technique as a feasible way to extend the cache lifetime up to 5X. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica |
dc.subject.lcsh | Random access memory |
dc.title | Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design |
dc.type | Article |
dc.subject.lemac | Memòria d'accés aleatori |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/TVLSI.2014.2355873 |
dc.description.peerreviewed | Peer Reviewed |
dc.rights.access | Open Access |
local.identifier.drac | 15374832 |
dc.description.version | Postprint (author’s final draft) |
local.citation.author | Pouyan, P.; Amat, Esteve; Rubio, A. |
local.citation.publicationName | IEEE transactions on very large scale integration (VLSI) systems |
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