Show simple item record

dc.contributor.authorPouyan, Peyman
dc.contributor.authorAmat Bertran, Esteve
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2015-01-13T10:48:43Z
dc.date.available2015-02-25T14:52:58Z
dc.date.created2014
dc.date.issued2014
dc.identifier.citationPouyan, P.; Amat, Esteve; Rubio, A. Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design. "IEEE transactions on very large scale integration (VLSI) systems", 2014.
dc.identifier.issn1063-8210
dc.identifier.urihttp://hdl.handle.net/2117/25262
dc.description.abstractNanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive reconfiguration is an emerging technique oriented to extend the system lifetime of memories affected by aging. In this brief, we present a new approach for static random access memory (SRAM) design that extends the cache lifetime when considering process variation and aging in the memory cells using an adaptive strategy. To track the aging in the SRAM cells we propose an on-chip monitoring technique. Our results show the technique as a feasible way to extend the cache lifetime up to 5X.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica
dc.subject.lcshRandom access memory
dc.titleAdaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design
dc.typeArticle
dc.subject.lemacMemòria d'accés aleatori
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/TVLSI.2014.2355873
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
drac.iddocument15374832
dc.description.versionPostprint (author’s final draft)
upcommons.citation.authorPouyan, P.; Amat, Esteve; Rubio, A.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIEEE transactions on very large scale integration (VLSI) systems


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder