Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
European Commisision's projectROMOL - Riding on Moore's Law (EC-FP7-321253)
Graph500 is a data intensive application for high performance computing and it is an increasingly important workload because graphs are a core part of most analytic applications. So far there is no work that examines if Graph500 is suitable for vectorization mostly due a lack of vector memory instructions for irregular memory accesses. The Xeon Phi is a massively parallel processor recently released by Intel with new features such as a wide 512-bit vector unit and vector scatter/gather instructions. Thus, the Xeon Phi allows for more efficient parallelization of Graph500 that is combined with vectorization. In this paper we vectorize Graph500 and analyze the impact of vectorization and prefetching on the Xeon Phi. We also show that the combination of parallelization, vectorization and prefetching yields a speedup of 27% over a parallel version with prefetching that does not leverage the vector capabilities of the Xeon Phi.
CitationStanic, M. [et al.]. Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi. A: International Conference on High Performance Computing & Simulation. "Proceedings of the 2014 International Conference on High Performance Computing and Simulation: July 21-25, 2014, Bologna, Italy". Bologna: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 47-54.
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