Interleaved Scrambling Technique: A Novel Low-Power Security Layer for Cache Memories
Tipus de documentComunicació de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés restringit per política de l'editorial
Memory systems security has increased over the last decade due to the sensitive information which is stored in plain text. Device specific attacks, such as cold-boot and sidechannel monitoring have been reported as being successfully in retrieving encryption and private keys from algorithms like AES and RSA. In this paper, we propose a new technique of securing the cache memories by scrambling the stored data that uses interleaved scrambling vectors which reduce the power consumption if compared to the standard scrambling technique. Dissemination rules for the retained data in the cache are employed, in order to make data unusable if retrieved successfully by any type of attack. The proposed technique is analyzed and evaluated from several points of views, including area overhead, power consumption and time performance.
CitacióNeagu, M.; Manich, S.; Miclea, L. Interleaved Scrambling Technique: A Novel Low-Power Security Layer for Cache Memories. A: IEEE European Test Symposium. "19th IEEE European Test Symposium: May 26-30, 2014: ETS 2010, Praga: digest of papers". Paderborn: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 1-2.