All-digital simple clock synthesis through a glitch-free variable-length ring oscillator
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This brief presents a simple all-digital variable-length ring oscillator (VLRO) design that is capable of synchronously changing the output frequency while keeping a signal free of glitches or spurious oscillations at the frequency transitions. The correct operation of the proposed VLRO has been experimentally validated on a 90-nm Xilinx Spartan-3E field-programmable gate array, showing the ability to switch between 16 different frequencies (from 24.1 to 321 MHz for the nominal core supply voltage) under different supply voltages with the expected behavior.
CitationPerez, J.; Moll, F.; Calomarde, A. All-digital simple clock synthesis through a glitch-free variable-length ring oscillator. "IEEE transactions on circuits and systems II: express briefs", 01 Febrer 2014, vol. 61, núm. 2, p. 90-94.
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