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dc.contributor.authorHussain, Tassadaq
dc.contributor.authorPalomar Pérez, Óscar
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2014-11-11T13:38:03Z
dc.date.created2014
dc.date.issued2014
dc.identifier.citationHussain, T. [et al.]. PVMC: Programmable Vector Memory Controller. A: International Conference on Application-Specific Systems, Architectures and Processors. "2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors: (ASAP 2014): 18-20 June 2014: Zurich, Switzerland". Zurich: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 240-247.
dc.identifier.isbn978-1-4799-3608-3
dc.identifier.urihttp://hdl.handle.net/2117/24680
dc.description.abstractIn this work, we propose a Programmable Vector Memory Controller (PVMC), which boosts noncontiguous vector data accesses by integrating descriptors of memory patterns, a specialized local memory, a memory manager in hardware, and multiple DRAM controllers. We implemented and validated the proposed system on an Altera DE4 FPGA board. We compare the performance of our proposal with a vector system without PVMC as well as a scalar only system. When compared with a baseline vector system, the results show that the PVMC system transfers data sets up to 2.2× to 14.9× faster, achieves between 2.16× to 3.18× of speedup for 5 applications and consumes 2.56 to 4.04 times less energy. © 2014 IEEE.
dc.description.sponsorshipThe research leading to these results has received funding from the European Research Council under the European Unions 7th FP (FP/2007-2013) / ERC GA n. 321253. It has been partially funded by the Spanish Government (TIN2012-34557).
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures distribuïdes
dc.subjectÀrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació
dc.subject.lcshRandom access memory
dc.subject.lcshMemory management (Computer science)
dc.subject.otherComputer architecture
dc.subject.otherControllers
dc.subject.otherDynamic random access storage
dc.subject.otherBaseline vectors
dc.subject.otherFPGA boards
dc.subject.otherLocal memory
dc.subject.otherMemory controller
dc.subject.otherMemory manager
dc.subject.otherMemory patterns
dc.subject.otherVector data
dc.subject.otherVector systems
dc.subject.otherVectors
dc.titlePVMC: Programmable Vector Memory Controller
dc.typeConference report
dc.subject.lemacGestió de memòria (Informàtica)
dc.subject.lemacOrdinadors -- Dispositius de memòria
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/ASAP.2014.6868668
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6868668
dc.rights.accessOpen Access
local.identifier.drac15225911
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
dc.date.lift10000-01-01
local.citation.authorHussain, T.; Palomar, O.; Unsal, O.; Cristal, A.; Ayguade, E.; Valero, M.
local.citation.contributorInternational Conference on Application-Specific Systems, Architectures and Processors
local.citation.pubplaceZurich
local.citation.publicationName2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors: (ASAP 2014): 18-20 June 2014: Zurich, Switzerland
local.citation.startingPage240
local.citation.endingPage247


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