PVMC: Programmable Vector Memory Controller
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
European Commission's projectROMOL - Riding on Moore's Law (EC-FP7-321253)
In this work, we propose a Programmable Vector Memory Controller (PVMC), which boosts noncontiguous vector data accesses by integrating descriptors of memory patterns, a specialized local memory, a memory manager in hardware, and multiple DRAM controllers. We implemented and validated the proposed system on an Altera DE4 FPGA board. We compare the performance of our proposal with a vector system without PVMC as well as a scalar only system. When compared with a baseline vector system, the results show that the PVMC system transfers data sets up to 2.2× to 14.9× faster, achieves between 2.16× to 3.18× of speedup for 5 applications and consumes 2.56 to 4.04 times less energy. © 2014 IEEE.
CitationHussain, T. [et al.]. PVMC: Programmable Vector Memory Controller. A: International Conference on Application-Specific Systems, Architectures and Processors. "2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors: (ASAP 2014): 18-20 June 2014: Zurich, Switzerland". Zurich: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 240-247.
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder