On the selection of adder unit in energy efficient vector processing
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés restringit per política de l'editorial
Projecte de la Comissió EuropeaHIPEAC - High Performance and Embedded Architecture and Compilation (EC-FP7-287759)
Vector processors are a very promising solution for mobile devices and servers due to their inherently energy-efficient way of exploiting data-level parallelism. Previous research on vector architectures predominantly focused on performance, so vector processors require a new design space exploration to achieve low power. In this paper, we present a design space exploration of adder unit for vector processors (VA), as it is one of the crucial components in the core design with a non-negligible impact in overall performance and power. For this interrelated circuit-architecture exploration, we developed a novel framework with both architectural- and circuit-level tools. Our framework includes both design- (e.g. adder's family type) and vector architecture-related parameters (e.g. vector length). Finally, we present guidelines on the selection of the most appropriate VA for different types of vector processors according to different sets of metrics of interest. For example, we found that 2-lane configurations are more EDP (Energy×Delay)-efficient than single lane configurations for low-end mobile processors.
CitacióRatkovic, I. [et al.]. On the selection of adder unit in energy efficient vector processing. A: International Symposium on Quality Electronic Design. "Proceedings of the Fourteenth International Symposium on Quality Electronic Design: ISQED 2013: March 4-6, 2013: Santa Clara, California, USA". Santa Clara, California: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 143-150.
Versió de l'editorhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6523602
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