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Post-Bond test of through-silicon vias with open defects
dc.contributor.author | Rodríguez Montañés, Rosa |
dc.contributor.author | Arumi Delgado, Daniel |
dc.contributor.author | Figueras Pàmies, Joan |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2014-11-10T10:54:53Z |
dc.date.created | 2014 |
dc.date.issued | 2014 |
dc.identifier.citation | Rodriguez, R.; Arumi, D.; Figueras, J. Post-Bond test of through-silicon vias with open defects. A: IEEE European Test Symposium. "PROCEEDINGS 19TH IEEE EUROPEAN TEST SYMPOSIUM". Paderborn: 2014, p. 1-6. |
dc.identifier.isbn | 978-1-4799-3414-0 |
dc.identifier.uri | http://hdl.handle.net/2117/24629 |
dc.description.abstract | Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement, pinholes in the oxide or misalignments during bonding in such a way that resistive opens become a frequent failure mechanism affecting TSVs. Although there is considerable research effort dedicated to improve TSVs testing, no much attention has been paid to weak defects, especially to weak open defects (resistive opens) causing small delays. In this work, a testing strategy is proposed to detect small delay defects by means of a post-bond oscillation test. Variations in the Duty Cycle of transmitted signals after unbalanced logic gates are shown to detect weak open defects in TSVs. HSPICE simulations including process parameter variations show the effectiveness of the method in the detection of weak open defects above 1 kO. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Integrated circuits--Design and construction |
dc.subject.lcsh | Integrated circuits--Testing |
dc.subject.other | 3-D IC |
dc.subject.other | Through-Silicon Via (TSV) |
dc.subject.other | resistive open defect |
dc.subject.other | TSV testing |
dc.subject.other | duty cycle |
dc.subject.other | design for testability |
dc.title | Post-Bond test of through-silicon vias with open defects |
dc.type | Conference report |
dc.subject.lemac | Circuits integrats digitals -- Disseny i construcció |
dc.subject.lemac | Circuits integrats -- Testeig |
dc.contributor.group | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.identifier.doi | 10.1109/ETS.2014.6847816 |
dc.relation.publisherversion | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6847816 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 14989894 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Rodriguez, R.; Arumi, D.; Figueras, J. |
local.citation.contributor | IEEE European Test Symposium |
local.citation.pubplace | Paderborn |
local.citation.publicationName | PROCEEDINGS 19TH IEEE EUROPEAN TEST SYMPOSIUM |
local.citation.startingPage | 1 |
local.citation.endingPage | 6 |