Mostra el registre d'ítem simple
EVX: vector execution on low power EDGE cores
dc.contributor.author | Duric, Milovan |
dc.contributor.author | Palomar Pérez, Óscar |
dc.contributor.author | Smith, Aaron |
dc.contributor.author | Unsal, Osman Sabri |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Burger, Doug |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2014-11-06T18:32:10Z |
dc.date.created | 2014 |
dc.date.issued | 2014 |
dc.identifier.citation | Duric, M. [et al.]. EVX: vector execution on low power EDGE cores. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014". Dreden: European Interactive Digital Advertising Alliance (EDAA), 2014, p. 1-4. |
dc.identifier.isbn | 978-398153702-4 |
dc.identifier.uri | http://hdl.handle.net/2117/24585 |
dc.description.abstract | In this paper, we present a vector execution model that provides the advantages of vector processors on low power, general purpose cores, with limited additional hardware. While accelerating data-level parallel (DLP) workloads, the vector model increases the efficiency and hardware resources utilization. We use a modest dual issue core based on an Explicit Data Graph Execution (EDGE) architecture to implement our approach, called EVX. Unlike most DLP accelerators which utilize additional hardware and increase the complexity of low power processors, EVX leverages the available resources of EDGE cores, and with minimal costs allows for specialization of the resources. EVX adds a control logic that increases the core area by 2.1%. We show that EVX yields an average speedup of 3x compared to a scalar baseline and outperforms multimedia SIMD extensions. © 2014 EDAA. |
dc.format.extent | 4 p. |
dc.language.iso | eng |
dc.publisher | European Interactive Digital Advertising Alliance (EDAA) |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Hardware |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Multiprocessors |
dc.subject.lcsh | Vector processing (Computer science) |
dc.subject.other | Power aware computing |
dc.subject.other | Vector processor systems |
dc.subject.other | DLP workloads |
dc.subject.other | EVX |
dc.subject.other | Data-level parallel workloads |
dc.subject.other | Explicit data graph execution architecture |
dc.subject.other | Hardware resources utilization |
dc.subject.other | Low power EDGE cores |
dc.subject.other | Vector execution model |
dc.subject.other | Vector processors |
dc.subject.other | Computational modeling |
dc.subject.other | Computer architecture |
dc.subject.other | Hardware |
dc.subject.other | Kernel |
dc.subject.other | Program processors |
dc.subject.other | Registers |
dc.subject.other | Vectors |
dc.title | EVX: vector execution on low power EDGE cores |
dc.type | Conference report |
dc.subject.lemac | Multiprocessadors |
dc.subject.lemac | Arquitectura d'ordinadors |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.7873/DATE.2014.035 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6800236 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 15144363 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Duric, M.; Palomar, O.; Smith, A.; Unsal, O.; Cristal, A.; Valero, M.; Burger, D. |
local.citation.contributor | Design, Automation and Test in Europe |
local.citation.pubplace | Dreden |
local.citation.publicationName | Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014 |
local.citation.startingPage | 1 |
local.citation.endingPage | 4 |