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dc.contributor.authorDuric, Milovan
dc.contributor.authorPalomar Pérez, Óscar
dc.contributor.authorSmith, Aaron
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorBurger, Doug
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-11-06T18:32:10Z
dc.date.created2014
dc.date.issued2014
dc.identifier.citationDuric, M. [et al.]. EVX: vector execution on low power EDGE cores. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014". Dreden: European Interactive Digital Advertising Alliance (EDAA), 2014, p. 1-4.
dc.identifier.isbn978-398153702-4
dc.identifier.urihttp://hdl.handle.net/2117/24585
dc.description.abstractIn this paper, we present a vector execution model that provides the advantages of vector processors on low power, general purpose cores, with limited additional hardware. While accelerating data-level parallel (DLP) workloads, the vector model increases the efficiency and hardware resources utilization. We use a modest dual issue core based on an Explicit Data Graph Execution (EDGE) architecture to implement our approach, called EVX. Unlike most DLP accelerators which utilize additional hardware and increase the complexity of low power processors, EVX leverages the available resources of EDGE cores, and with minimal costs allows for specialization of the resources. EVX adds a control logic that increases the core area by 2.1%. We show that EVX yields an average speedup of 3x compared to a scalar baseline and outperforms multimedia SIMD extensions. © 2014 EDAA.
dc.format.extent4 p.
dc.language.isoeng
dc.publisherEuropean Interactive Digital Advertising Alliance (EDAA)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors
dc.subject.lcshVector processing (Computer science)
dc.subject.otherPower aware computing
dc.subject.otherVector processor systems
dc.subject.otherDLP workloads
dc.subject.otherEVX
dc.subject.otherData-level parallel workloads
dc.subject.otherExplicit data graph execution architecture
dc.subject.otherHardware resources utilization
dc.subject.otherLow power EDGE cores
dc.subject.otherVector execution model
dc.subject.otherVector processors
dc.subject.otherComputational modeling
dc.subject.otherComputer architecture
dc.subject.otherHardware
dc.subject.otherKernel
dc.subject.otherProgram processors
dc.subject.otherRegisters
dc.subject.otherVectors
dc.titleEVX: vector execution on low power EDGE cores
dc.typeConference report
dc.subject.lemacMultiprocessadors
dc.subject.lemacArquitectura d'ordinadors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.7873/DATE.2014.035
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6800236
dc.rights.accessRestricted access - publisher's policy
drac.iddocument15144363
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorDuric, M.; Palomar, O.; Smith, A.; Unsal, O.; Cristal, A.; Valero, M.; Burger, D.
upcommons.citation.contributorDesign, Automation and Test in Europe
upcommons.citation.pubplaceDreden
upcommons.citation.publishedtrue
upcommons.citation.publicationNameDesign, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014
upcommons.citation.startingPage1
upcommons.citation.endingPage4


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Except where otherwise noted, content on this work is licensed under a Creative Commons license: Attribution-NonCommercial-NoDerivs 3.0 Spain