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dc.contributor.authorUpasani, Gaurang
dc.contributor.authorVera Rivera, Francisco Javier
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-11-06T13:58:50Z
dc.date.created2014
dc.date.issued2014
dc.identifier.citationUpasani, G.; Vera, X.; González, A. Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery. A: International Symposium on Computer Architecture. "ISCA 2014: the 41st Annual International Symposium on Computer Architecture: June 14-18, 2014: Minneapolis, MN, USA". Minneapolis: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 37-48.
dc.identifier.isbn978-147994396-8
dc.identifier.urihttp://hdl.handle.net/2117/24576
dc.description.abstractThe trend of downsizing transistors and operating voltage scaling has made the processor chip more sensitive against radiation phenomena making soft errors an important challenge. New reliability techniques for handling soft errors in the logic and memories that allow meeting the desired failures-in-time (FIT) target are key to keep harnessing the benefits of Moore's law. The failure to scale the soft error rate caused by particle strikes, may soon limit the total number of cores that one may have running at the same time. This paper proposes a light-weight and scalable architecture to eliminate silent data corruption errors (SDC) and detected unrecoverable errors (DUE) of a core. The architecture uses acoustic wave detectors for error detection. We propose to recover by confining the errors in the cache hierarchy, allowing us to deal with the relatively long detection latencies. Our results show that the proposed mechanism protects the whole core (logic, latches and memory arrays) incurring performance overhead as low as 0.60%. © 2014 IEEE.
dc.format.extent12 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subjectÀrees temàtiques de la UPC::Enginyeria de la telecomunicació::Radiocomunicació i exploració electromagnètica
dc.subject.lcshMicroprocessors
dc.subject.lcshSound-waves
dc.subject.otherAcoustic waves
dc.subject.otherAcoustics
dc.subject.otherComputer architecture
dc.subject.otherError correction
dc.subject.otherRadiation hardening
dc.subject.otherVoltage scaling
dc.subject.otherCache hierarchies
dc.subject.otherDetected unrecoverable errors
dc.subject.otherDetection latency
dc.subject.otherOperating voltage
dc.subject.otherReliability techniques
dc.subject.otherScalable architectures
dc.subject.otherSilent data corruptions
dc.subject.otherSoft error rate
dc.subject.otherMicroprocessor chips
dc.titleAvoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery
dc.typeConference report
dc.subject.lemacMicroprocessadors
dc.subject.lemacOnes sonores
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/ISCA.2014.6853200
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6853200
dc.rights.accessOpen Access
drac.iddocument15248572
dc.description.versionPostprint (author's final draft)
dc.date.lift10000-01-01
upcommons.citation.authorUpasani, G.; Vera, X.; González, A.
upcommons.citation.contributorInternational Symposium on Computer Architecture
upcommons.citation.pubplaceMinneapolis
upcommons.citation.publishedtrue
upcommons.citation.publicationNameISCA 2014: the 41st Annual International Symposium on Computer Architecture: June 14-18, 2014: Minneapolis, MN, USA
upcommons.citation.startingPage37
upcommons.citation.endingPage48


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