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dc.contributor.authorLandauer, Gerhard Martin
dc.contributor.authorGonzález Jiménez, José Luis
dc.contributor.authorJiménez Jiménez, David
dc.date.accessioned2014-10-17T08:29:10Z
dc.date.created2014-06-04
dc.date.issued2014-06-04
dc.identifier.citationLandauer, G.M.; González, J.L.; Jiménez, D. An accurate and Verilog-A compatible compact model for graphene field-effect transistors. "IEEE transactions on nanotechnology", 04 Juny 2014, vol. 13, núm. 5, p. 895-904.
dc.identifier.issn1536-125X
dc.identifier.urihttp://hdl.handle.net/2117/24401
dc.description.abstractThe present paper provides an accurate drift-diffusion model of the graphene field-effect transistor (GFET). A precise yet mathematically simple current-voltage relation is derived by focusing on device physics at energy levels close to the Dirac point. With respect to previous work, our approach extends modeling accuracy to the low-voltage biasing regime and improves the prediction of current saturation. These advantages are highlighted by a comparison study of the drain current, transconductance, output conductance, and intrinsic gain. The model has been implemented in Verilog-A and is compatible with conventional circuit simulators. It is provided as a tool for the exploration of GFET-based integrated circuit design. The model shows good agreement with measurement data from GFET prototypes.
dc.format.extent10 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subject.lcshNanotechnology
dc.subject.otherDirac point
dc.subject.otherGFET-based integrated circuit design
dc.subject.otherVerilog-A compatible compact model
dc.subject.othercircuit simulators
dc.subject.othercurrent saturation
dc.subject.othercurrent-voltage relation
dc.subject.otherdrain current
dc.subject.otherdrift-diffusion model
dc.subject.otherenergy levels
dc.subject.othergraphene field-effect transistor
dc.subject.otherintrinsic gain
dc.subject.otherlow-voltage biasing regime
dc.subject.otheroutput conductance
dc.subject.othertransconductance
dc.titleAn accurate and Verilog-A compatible compact model for graphene field-effect transistors
dc.typeArticle
dc.subject.lemacNanotecnologia
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/TNANO.2014.2328782
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6825842
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac15250511
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorLandauer, G.M.; González, J.L.; Jiménez, D.
local.citation.publicationNameIEEE transactions on nanotechnology
local.citation.volume13
local.citation.number5
local.citation.startingPage895
local.citation.endingPage904


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