Analysis and modelling of parasitic substrate coupling in CMOS circuits
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Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling tendencies of IC scaling are analysed, following interest in advanced technologies. The potential for permanent errors is shown in the case of a RAM cell. A circuit-level model for the coupling mechanism is proposed. The implementation of an IC for experimentation, and the measurements obtained, are discussed
CitationAragones, X. [et al.]. Analysis and modelling of parasitic substrate coupling in CMOS circuits. "IEE proceedings-Circuits devices and systems", Octubre 1995, vol. 142, núm. 5, p. 307-312.
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