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Metastability in better-than-worst-case designs
| dc.contributor.author | Beer, Salomon |
| dc.contributor.author | Cannizzaro, Marco |
| dc.contributor.author | Cortadella, Jordi |
| dc.contributor.author | Ginosar, Ran |
| dc.contributor.author | Lavagno, Luciano |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
| dc.date.accessioned | 2014-09-26T10:14:18Z |
| dc.date.available | 2014-09-26T10:14:18Z |
| dc.date.created | 2014 |
| dc.date.issued | 2014 |
| dc.identifier.citation | Beer, S. [et al.]. Metastability in better-than-worst-case designs. A: International Symposium on Asynchronous Circuits and Systems. "20th IEEE International Symposium on Asynchronous Circuits and Systems: 12–14 May 2014, Potsdam, Germany: proceedings". Potsdam: Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 101-102. |
| dc.identifier.isbn | 978-147993789-9 |
| dc.identifier.uri | http://hdl.handle.net/2117/24174 |
| dc.description.abstract | Better-Than-Worst-Case-Designs use timing speculation to run with a cycle period faster than the one required for worst-case conditions. This speculation may produce timing violations and metastability that result in failures and non-deterministic timing behavior. The effects of these phenomena are not always well understood by designers and researchers in this area. This paper analyzes the impact of timing speculation and the reasons why it is difficult to adopt this paradigm in industrial designs. |
| dc.format.extent | 2 p. |
| dc.language.iso | eng |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics |
| dc.subject.lcsh | Electronic circuits |
| dc.subject.other | Metastability |
| dc.subject.other | Better-than-worst-case designs |
| dc.subject.other | Timing violations |
| dc.subject.other | Nondeterministic timing behavior: Timing speculation |
| dc.subject.other | Industrial designs |
| dc.title | Metastability in better-than-worst-case designs |
| dc.type | Conference report |
| dc.subject.lemac | Circuits electrònics |
| dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
| dc.identifier.doi | 10.1109/ASYNC.2014.21 |
| dc.relation.publisherversion | https://ieeexplore.ieee.org/document/6835817 |
| dc.rights.access | Open Access |
| local.identifier.drac | 15142939 |
| dc.description.version | Postprint (author’s final draft) |
| local.citation.author | Beer, S.; Cannizzaro, M.; Cortadella, J.; Ginosar, R.; Lavagno, L. |
| local.citation.contributor | International Symposium on Asynchronous Circuits and Systems |
| local.citation.pubplace | Potsdam |
| local.citation.publicationName | 20th IEEE International Symposium on Asynchronous Circuits and Systems: 12–14 May 2014, Potsdam, Germany: proceedings |
| local.citation.startingPage | 101 |
| local.citation.endingPage | 102 |
