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dc.contributor.authorGanapathy, Shrikanth
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2014-09-10T07:44:48Z
dc.date.created2010
dc.date.issued2010
dc.identifier.citationGanapathy, S. [et al.]. MODEST: a model for energy estimation under spatio-temporal variability. A: International Symposium on Low Power Electronics and Design. "ISLPED '10: Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design". Austin, TX: Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 129-134.
dc.identifier.isbn978-1-4503-0146-6
dc.identifier.urihttp://hdl.handle.net/2117/24024
dc.description.abstractEstimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental conditions which makes the problem of energy estimation more dynamic in nature. It is worsened by process induced variations of low level parameters like threshold voltage and channel length. In this paper we present MODEST, a proposal for estimating the static and dynamic energy of caches taking into account spatial variations of physical parameters, temporal changes of supply voltage and environmental factors like temperature. It can be used to estimate the energy of different blocks of a cache based on a combination empirical data and analytical equations. The observed maximum and median error between MODEST and HSPICE energy-estimates for 22,500 samples is around 7.8% and 0.5% respectively. As a case study, using MODEST, we propose a two step iterative optimization procedure involving Dual-Vth assignment and standby supply voltage minimization for reclaiming energy-constrained caches. The observed energy reduction is around 50.8% for the most-leaky Cache. A speed-up of 750X over conventional hard-coded implementation for such optimizations is achieved.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshCache memory
dc.subject.lcshIntegrated circuits -- Design and construction
dc.subject.otherCache Design
dc.subject.otherSpatio-temporal variability
dc.subject.otherDSM scaling
dc.titleMODEST: a model for energy estimation under spatio-temporal variability
dc.typeConference report
dc.subject.lemacMemòria cau
dc.subject.lemacCircuits integrats -- Disseny i construcció
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://portal.acm.org/citation.cfm?id=1840845.1840873
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac4436066
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorGanapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A.
local.citation.contributorInternational Symposium on Low Power Electronics and Design
local.citation.pubplaceAustin, TX
local.citation.publicationNameISLPED '10: Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design
local.citation.startingPage129
local.citation.endingPage134


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