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dc.contributor.authorGanapathy, Shrikanth
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2014-09-10T07:36:08Z
dc.date.created2010
dc.date.issued2010
dc.identifier.citationGanapathy, S. [et al.]. Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. A: Design, Automation and Test in Europe. "Design, Automation & Test in Europe: Dresden, Germany, March 8-12, 2010: proceedings". Dresden: Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 417-422.
dc.identifier.isbn978-3-9810801-6-2
dc.identifier.urihttp://hdl.handle.net/2117/24023
dc.description.abstractWith every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit performance are likely to suffer the most from this phenomena. While Statistical static timing analysis (SSTA) is used extensively for this purpose, it does not account for dynamic conditions during operation. In this paper, we present a multivariate regression based technique that computes the propagation delay of circuits subject to manufacturing process variations in the presence of temporal variations like temperature. It can be used to predict the dynamic behavior of circuits under changing operating conditions. The median error between the proposed model and circuit-level simulations is below 5%. With this model, we ran a study of the effect of temperature on access time delays for 500 cache samples. The study was run in 0.557 seconds, compared to the 20h and 4min of the SPICE simulation achieving a speedup of over 1??105. As a case study, we show that the access times of caches can vary as much as 2.03?? at high temperatures in future technologies under process variations.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshIntegrated circuits -- Design and construction
dc.subject.otherCache storage
dc.subject.otherDelays
dc.subject.otherIntegrated circuit modelling
dc.subject.otherRegression analysis
dc.subject.otherTiming
dc.titleCircuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
dc.typeConference report
dc.subject.lemacCircuits integrats -- Disseny i construcció
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/DATE.2010.5457167
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac4435294
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorGanapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A.
local.citation.contributorDesign, Automation and Test in Europe
local.citation.pubplaceDresden
local.citation.publicationNameDesign, Automation & Test in Europe: Dresden, Germany, March 8-12, 2010: proceedings
local.citation.startingPage417
local.citation.endingPage422


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