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dc.contributor.authorFoutris, Nikos
dc.contributor.authorPsarakis, M.
dc.contributor.authorGizopoulos, Dimitris
dc.contributor.authorApostolakis, A.
dc.contributor.authorVera Rivera, Francisco Javier
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-09-08T09:33:04Z
dc.date.available2014-09-08T09:33:04Z
dc.date.created2010
dc.date.issued2010
dc.identifier.citationFoutris, N. [et al.]. MT-SBST: self-test optimization in multithreaded multicore architectures. A: IEEE International Test Conference. "Proceedings: International Test Conference 2010". Austin, TX: Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 1-10.
dc.identifier.isbn978-1-4244-7206-2
dc.identifier.urihttp://hdl.handle.net/2117/23998
dc.description.abstractInstruction-based or software-based self-testing (SBST) is a scalable functional testing paradigm that has gained increasing acceptance in testing of single-threaded uniprocessors. Recent computer architecture trends towards chip multiprocessing and multithreading have raised new challenges in the test process. In this paper, we present a novel self-test optimization strategy for multithreaded, multicore microprocessor architectures and apply it to both manufacturing testing (execution from on-chip cache memory) and post-silicon validation (execution from main memory) setups. The proposed self-test program execution optimization aims to: (a) take maximum advantage of the available execution parallelism provided by multiple threads and multiple cores, (b) preserve the high fault coverage that single-thread execution provides for the processor components, and (c) enhance the fault coverage of the thread-specific control logic of the multithreaded multiprocessor. The proposed multithreaded (MT) SBST methodology generates an efficient multithreaded version of the test program and schedules the resulting test threads into the hardware threads of the processor to reduce the overall test execution time and on the same time to increase the overall fault coverage. We demonstrate our methodology in the OpenSPARC T1 processor model which integrates eight CPU cores, each one supporting four hardware threads. MT-SBST methodology and scheduling algorithm significantly speeds up self-test time at both the core level (3.6 times) and the processor level (6.0 times) against single-threaded execution, while at the same time it improves the overall fault coverage. Compared with straightforward multithreaded execution, it reduces the self-test time at both the core level and the processor level by 33% and 20%, respectively. Overall, MT-SBST reaches more than 91% stuck-at fault coverage for the functional units and 88% for the entire chip multiprocessor, a total of more than 1.5M logic gates.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMicroprocessors
dc.subject.otherBuilt-in self test
dc.subject.otherElectronic engineering computing
dc.subject.otherMicroprocessor chips
dc.subject.otherMulti-threading
dc.subject.otherMultiprocessing systems
dc.titleMT-SBST: self-test optimization in multithreaded multicore architectures
dc.typeConference report
dc.subject.lemacMicroprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/TEST.2010.5699277
dc.rights.accessOpen Access
drac.iddocument5276973
dc.description.versionPostprint (published version)
upcommons.citation.authorFoutris, N.; Psarakis, M.; Gizopoulos, D.; Apostolakis, A.; Vera, X.; Gonzalez, A.
upcommons.citation.contributorIEEE International Test Conference
upcommons.citation.pubplaceAustin, TX
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings: International Test Conference 2010
upcommons.citation.startingPage1
upcommons.citation.endingPage10


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