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Control-flow speculation through value prediction
dc.contributor.author | González, José |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2014-09-05T10:45:10Z |
dc.date.created | 2001-12 |
dc.date.issued | 2001-12 |
dc.identifier.citation | González, J.; Gonzalez, A. Control-flow speculation through value prediction. "IEEE transactions on computers", Desembre 2001, vol. 50, núm. 12, p. 1362-1376. |
dc.identifier.issn | 0018-9340 |
dc.identifier.uri | http://hdl.handle.net/2117/23987 |
dc.description.abstract | In this paper, we introduce a new branch predictor that predicts the outcome of branches by predicting the value of their inputs and performing an early computation of their results according to the predicted values. The design of a hybrid predictor comprising the above branch predictor and a correlating branch predictor is presented. We also propose a new selector that chooses the most reliable prediction for each branch. This selector is based on the path followed to reach the branch. Results for immediate updates show significant misprediction rate reductions with respect to a conventional hybrid predictor for different size configurations. In addition, the proposed hybrid predictor with a size of 8 KB achieves the same accuracy as a conventional one of 64 KB. Performance evaluation for a dynamically scheduled superscalar processor, with realistic updates, shows a speed up of 8 percent despite its higher latency (up to four cycles). |
dc.format.extent | 15 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Parallel processing (Electronic computers) |
dc.subject.other | Branch prediction |
dc.subject.other | Value prediction |
dc.subject.other | Hybrid predictor |
dc.subject.other | Path-based selector |
dc.subject.other | Superscalar processors |
dc.title | Control-flow speculation through value prediction |
dc.type | Article |
dc.subject.lemac | Processament en paral·lel (Ordinadors) |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/TC.2001.970574 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 14991696 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | González, J.; Gonzalez, A. |
local.citation.publicationName | IEEE transactions on computers |
local.citation.volume | 50 |
local.citation.number | 12 |
local.citation.startingPage | 1362 |
local.citation.endingPage | 1376 |
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