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dc.contributor.authorJalle Ibarra, Javier
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorQuiñones, Eduardo
dc.contributor.authorFossati, Luca
dc.contributor.authorZulianello, Marco
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-06-18T12:08:21Z
dc.date.created2013
dc.date.issued2013
dc.identifier.citationJalle, J. [et al.]. Deconstructing bus access control policies for real-time multicores. A: IEEE International Symposium on Industrial Embedded Systems. "Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems: SIES 2013: Porto, Portugal, June 19-21, 2013". Porto: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 31-38.
dc.identifier.isbn978-147990658-1
dc.identifier.urihttp://hdl.handle.net/2117/23259
dc.description.abstractMulticores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key role in system's performance and the tightness of the Worst-Case Execution Time (WCET) estimates. In this paper we develop analytical models of the contention that requests from different tasks running in different cores suffer for the two most-used contention control policies: Time-Division Multiple Access (TDMA) and Interference-Aware Bus Arbiter (IABA), which allows us to compare them. We further show the benefits of having such models for real-time system designers and chip providers. Our results show that WCET estimates obtained with TDMA are slightly (2%) tighter than those obtained with IABA, at the cost of knowing the exact cycle at which every access of every task accesses the bus. However, average performance is 10% worse with TDMA than with IABA. Overall, IABA is the most appealing contention-control policy since it allows achieving tight WCET estimates and high average performance with little burden for the user.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshEmbedded computer systems
dc.subject.lcshMultiprocessors
dc.titleDeconstructing bus access control policies for real-time multicores
dc.typeConference report
dc.subject.lemacOrdinadors immersos, Sistemes d'
dc.subject.lemacMultiprocessadors
dc.identifier.doi10.1109/SIES.2013.6601468
dc.rights.accessRestricted access - publisher's policy
drac.iddocument12869149
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/287519/EU/Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability/PARMERASA
dc.date.lift10000-01-01
upcommons.citation.authorJalle, J.; Abella, J.; Quiñones, E.; Fossati, L.; Zulianello, M.; Cazorla, F.
upcommons.citation.contributorIEEE International Symposium on Industrial Embedded Systems
upcommons.citation.pubplacePorto
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings of the 8th IEEE International Symposium on Industrial Embedded Systems: SIES 2013: Porto, Portugal, June 19-21, 2013
upcommons.citation.startingPage31
upcommons.citation.endingPage38


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