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dc.contributor.authorMaric, Bojan
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-06-18T11:43:23Z
dc.date.available2014-06-18T11:43:23Z
dc.date.created2013
dc.date.issued2013
dc.identifier.citationMaric, B.; Abella, J.; Valero, M. Efficient cache architectures for reliable hybrid voltage operation using EDC codes. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: Grenoble, France, March 18 - 22, 2013". Grenoble: 2013, p. 917-920.
dc.identifier.isbn978-398153700-0
dc.identifier.urihttp://hdl.handle.net/2117/23258
dc.description.abstractSemiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 p) required for new market segments such as body, urban life and environment monitoring. Caches have been shown to be the highest energy and area consumer in those chips. This paper proposes a novel, hybrid-operation (high Vcc, ultra-low Vcc), single-Vcc domain cache architecture based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with Error Detection and Correction (EDC) features for high reliability and performance predictability. Our architecture is proven to largely outperform existing solutions in terms of energy and area.
dc.format.extent4 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCache memory
dc.subject.otherCaches
dc.subject.otherLow energy
dc.subject.otherReal-time
dc.subject.otherReliability
dc.titleEfficient cache architectures for reliable hybrid voltage operation using EDC codes
dc.typeConference report
dc.subject.lemacMemòria cau
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessOpen Access
local.identifier.drac12884521
dc.description.versionPostprint (author’s final draft)
local.citation.authorMaric, B.; Abella, J.; Valero, M.
local.citation.contributorDesign, Automation and Test in Europe
local.citation.pubplaceGrenoble
local.citation.publicationNameDesign, Automation and Test in Europe: Grenoble, France, March 18 - 22, 2013
local.citation.startingPage917
local.citation.endingPage920


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