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dc.contributor.authorYazdanpanah Ahmadabadi, Fahimeh
dc.contributor.authorJiménez González, Daniel
dc.contributor.authorÁlvarez Martínez, Carlos
dc.contributor.authorEtsion, Yoav
dc.contributor.authorBadia Sala, Rosa Maria
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.identifier.citationYazdanpanah, F. [et al.]. Analysis of the Task Superscalar architecture hardware design. A: International Conference on Computational Science. "2013 International Conference on Computational Science (Procedia Computer Science, 2013, v.18, p. 339-348)". Barcelona: Springer, 2013, p. 339-348.
dc.description.abstractIn this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing some dependent and non-dependent tasks with both base and improved hardware designs and present the simulation results compared with the results of the runtime implementation.
dc.description.sponsorshipThis work is supported by the Ministry of Science and Technology of Spain and the European Union (FEDER funds) under contract TIN2007-60625, by the Generalitat de Catalunya (contract 2009-SGR-980), and by the European FP7 project TERAFLUX id. 249013, http://www.tera We would also like to thank the Xilinx University Program for its hardware and software donations.
dc.format.extent10 p.
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subject.lcshVHDL (Computer hardware description language)
dc.subject.otherTask Superscalar
dc.subject.otherHardware task scheduler
dc.titleAnalysis of the Task Superscalar architecture hardware design
dc.typeConference report
dc.subject.lemacVHDL (Llenguatge de descripció de maquinari)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessOpen Access
dc.description.versionPostprint (author’s final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/249013/EU/Exploiting dataflow parallelism in Teradevice Computing/TERAFLUX
local.citation.authorYazdanpanah, F.; Jimenez, D.; Alvarez, C.; Etsion, Y.; Badia, R.M.
local.citation.contributorInternational Conference on Computational Science
local.citation.publicationName2013 International Conference on Computational Science (Procedia Computer Science, 2013, v.18, p. 339-348)

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