Analysis of the Task Superscalar architecture hardware design
Document typeConference report
Rights accessOpen Access
European Commission's projectTERAFLUX - Exploiting dataflow parallelism in Teradevice Computing (EC-FP7-249013)
In this paper, we analyze the operational flow of two hardware implementations of the Task Superscalar architecture. The Task Superscalar is an experimental task based dataflow scheduler that dynamically detects inter-task data dependencies, identifies task-level parallelism, and executes tasks in the out-of-order manner. In this paper, we present a base implementation of the Task Superscalar architecture, as well as a new design with improved performance. We study the behavior of processing some dependent and non-dependent tasks with both base and improved hardware designs and present the simulation results compared with the results of the runtime implementation.
CitationYazdanpanah, F. [et al.]. Analysis of the Task Superscalar architecture hardware design. A: International Conference on Computational Science. "2013 International Conference on Computational Science (Procedia Computer Science, 2013, v.18, p. 339-348)". Barcelona: Springer, 2013, p. 339-348.
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder