INFORMER: an integrated framework for early-stage memory robustness analysis
Document typeConference report
PublisherEuropean Interactive Digital Advertising Alliance (EDAA)
Rights accessRestricted access - publisher's policy
With the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware design paradigm requires a holistic perspective of memory-wide metrics such as yield, power and performance. However, accurate estimation of such metrics is largely dependent on circuit implementation styles, technology parameters and architecture-level specifics. In this paper, we propose a fully automated tool - INFORMER - that helps high-level designers estimate memory reliability metrics rapidly and accurately. The tool relies on accurate circuit-level simulations of failure mechanisms such as soft-errors and parametric failures. The statistics obtained can then help couple low-level metrics with higher-level design choices. A new technique for rapid estimation of low-probability failure events is also proposed. We present three use-cases of our prototype tool to demonstrate its diverse capabilities in autonomously guiding large SRAM based robust memory designs. © 2014 EDAA.
CitationGanapathy, S. [et al.]. INFORMER: an integrated framework for early-stage memory robustness analysis. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014". Dreden: European Interactive Digital Advertising Alliance (EDAA), 2014, p. 1-4.
- ARCO - Microarquitectura i Compiladors - Ponències/Comunicacions de congressos 
- HIPICS - High Performance Integrated Circuits and Systems - Ponències/Comunicacions de congressos 
- Departament d'Arquitectura de Computadors - Ponències/Comunicacions de congressos 
- Departament d'Enginyeria Electrònica - Ponències/Comunicacions de congressos 
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