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dc.contributor.authorJalle Ibarra, Javier
dc.contributor.authorKosmidis, Leonidas
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorQuiñones, Eduardo
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-06-11T16:48:34Z
dc.date.created2014
dc.date.issued2014
dc.identifier.citationJalle, J. [et al.]. Bus designs for time-probabilistic multicore processors. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014". Dreden: European Interactive Digital Advertising Alliance (EDAA), 2014.
dc.identifier.isbn978-398153702-4
dc.identifier.urihttp://hdl.handle.net/2117/23203
dc.description.abstractProbabilistic Timing Analysis (PTA) reduces the amount of information needed to provide tight WCET estimates in real-time systems with respect to classic timing analysis. PTA imposes new requirements on hardware design that have been shown implementable for single-core architectures. However, no support has been proposed for multicores so far. In this paper, we propose several probabilistically-analysable bus designs for multicore processors ranging from 4 cores connected with a single bus, to 16 cores deploying a hierarchical bus design. We derive analytical models of the probabilistic timing behaviour for the different bus designs, show their suitability for PTA and evaluate their hardware cost. Our results show that the proposed bus designs (i) fulfil PTA requirements, (ii) allow deriving WCET estimates with the same cost and complexity as in single-core processors, and (iii) provide higher guaranteed performance than single-core processors, 3.4x and 6.6x on average for an 8-core and a 16-core setup respectively.
dc.language.isoeng
dc.publisherEuropean Interactive Digital Advertising Alliance (EDAA)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshMultiprocessors
dc.subject.otherEngineering controlled terms: Buses
dc.subject.otherCost benefit analysis
dc.subject.otherHardware
dc.subject.otherReal time systems
dc.titleBus designs for time-probabilistic multicore processors
dc.typeConference report
dc.subject.lemacMultiprocessadors
dc.identifier.doi10.7873/DATE2014.063
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://dl.acm.org/citation.cfm?id=2616668
dc.rights.accessRestricted access - publisher's policy
drac.iddocument14920674
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorJalle, J.; Kosmidis, L.; Abella, J.; Quiñones, E.; Cazorla, F.
upcommons.citation.contributorDesign, Automation and Test in Europe
upcommons.citation.pubplaceDreden
upcommons.citation.publishedtrue
upcommons.citation.publicationNameDesign, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014


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Except where otherwise noted, content on this work is licensed under a Creative Commons license: Attribution-NonCommercial-NoDerivs 3.0 Spain