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dc.contributor.authorJaksic, Zoran
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-06-11T16:42:31Z
dc.date.created2014
dc.date.issued2014
dc.identifier.citationJaksic, Z.; Canal, R. DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014". Dreden: European Interactive Digital Advertising Alliance (EDAA), 2014.
dc.identifier.isbn978-398153702-4
dc.identifier.urihttp://hdl.handle.net/2117/23202
dc.description.abstractRecent technology trends has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these cells is that they lose their state (i.e. value) over time, and they have to be refreshed. This paper proposes the implementation of coherent caches with DRAM cells. Furthermore, we propose to use the coherence state to tune the refresh overhead. According to our analysis, an average of up to 57% of refresh energy can be saved. Also, comparing to the caches implemented in SRAMs total energy savings are on average up to 39% depending of the refresh policy with a performance loss below 8%.
dc.language.isoeng
dc.publisherEuropean Interactive Digital Advertising Alliance (EDAA)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors::Protocols de comunicació
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshMemory management (Computer science)
dc.subject.lcshEnergy conservation
dc.subject.other3T DRAM
dc.subject.other6T SRAM
dc.subject.othercache coherence
dc.subject.otherFinFETs
dc.subject.otherretention time
dc.titleDRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy
dc.typeConference report
dc.subject.lemacGestió de memòria (Informàtica)
dc.subject.lemacEnergia -- Estalvi
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.7873/DATE2014.094
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://dl.acm.org/citation.cfm?id=2616706
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac14920667
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorJaksic, Z.; Canal, R.
local.citation.contributorDesign, Automation and Test in Europe
local.citation.pubplaceDreden
local.citation.publicationNameDesign, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014


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Attribution-NonCommercial-NoDerivs 3.0 Spain
Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 3.0 Spain