DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy
Tipo de documentoTexto en actas de congreso
Fecha de publicación2014
EditorEuropean Interactive Digital Advertising Alliance (EDAA)
Condiciones de accesoAcceso restringido por política de la editorial
Recent technology trends has turned DRAMs into an interesting candidate to substitute traditional SRAM-based on-chip memory structures (i.e. register file, cache memories). Nevertheless, a major problem to introduce these cells is that they lose their state (i.e. value) over time, and they have to be refreshed. This paper proposes the implementation of coherent caches with DRAM cells. Furthermore, we propose to use the coherence state to tune the refresh overhead. According to our analysis, an average of up to 57% of refresh energy can be saved. Also, comparing to the caches implemented in SRAMs total energy savings are on average up to 39% depending of the refresh policy with a performance loss below 8%.
CitaciónJaksic, Z.; Canal, R. DRAM-based coherent caches and how to take advantage of the coherence protocol to reduce the refresh energy. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: proceedings: Dresden, Germany: March 24-28, 2014". Dreden: European Interactive Digital Advertising Alliance (EDAA), 2014.
Versión del editorhttp://dl.acm.org/citation.cfm?id=2616706
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