Circuit design of a novel adaptable and reliable L1 data cache
Document typeConference report
Rights accessOpen Access
European Commission's projectHIPEAC - High Performance and Embedded Architecture and Compilation (EC-FP7-287759)
This paper proposes a novel adaptable and reliable L1 data cache design (Adapcache) with the unique capability of automatically adapting itself for different supply voltage levels and providing the highest reliability. Depending on the supply voltage level, Adapcache defines three operating modes: In high supply voltages, Adapcache provides reliability through single-bit parity. In middle range of supply voltages, Adapcache writes data to two separate cache-lines simultaneously in order to use one line for error recovery when the other line is faulty. In near threshold supply voltages, Adapcache writes data to three separate cache-lines simultaneously in order to provide the correct data based on bitwise majority voter. We design and simulate one embodiment of the Adapcache as a 64-KB L1 data cache with 45-nm CMOS technology at 2GHz processor frequency for almost nominal supply voltages (1V-0.6V), at 900MHz for middle supply voltages (0.6V-0.4V), and at 400MHz for near threshold supply voltages (0.4V-0.32V). According to our experimental results, the energy reduction and latency as well as cache capacity usage are improved compared to typical previous proposals, Triple Modular Redundancy (TMR) and Double Modular Redundancy (DMR) techniques and also to the state of the art proposal, Parichute Error Correction Code (ECC).
CitationSeyedi, A. [et al.]. Circuit design of a novel adaptable and reliable L1 data cache. A: ACM Great Lakes Symposium on VLSI. "Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI". Parias: 2013, p. 333-334.
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