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dc.contributor.authorBrankovic, Aleksandar
dc.contributor.authorStavrou, K.
dc.contributor.authorGibert Codina, Enric
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-06-02T12:40:57Z
dc.date.created2014
dc.date.issued2014
dc.identifier.citationBrankovic, A. [et al.]. Warm-up simulation methodology for HW/SW co-designed processors. A: International Symposium on Code Generation and Optimization. "Proceedings of the 2014 CGO: the twelfth International Symposium on Code Generation and Optimization: February 15-19, 2014: Orlando, Florida". Orlando: ACM, 2014, p. 284-294.
dc.identifier.isbn978-1-4503-2670-4
dc.identifier.urihttp://hdl.handle.net/2117/23123
dc.description.abstractEvaluation techniques in microprocessor design are mostly based on simulating selected application samples using a cycle-accurate simulator. In order to achieve accurate results, microarchitectural structures are warmed-up for a few million instructions prior to statistics collection. Unfortunately, this strategy cannot be applied to HW/SW co-designed processors, in which a Transparent Optimization software Layer (TOL) translates and optimizes code on-the-fly from a guest ISA to an internal host custom microarchitecture. We show that the warm-up period in this case needs to be 3-4 orders of magnitude longer than what is needed for traditional microprocessor designs because the TOL state needs to be warmed-up as well. In this paper, we propose a novel simulation technique for HW/SW co-designed processors based on adapting the optimization promotion thresholds using high level application statistics in order to find the best trade-off between accuracy and simulation cost. In particular, the proposed technique reduces the simulation cost by 65X with an average error of just 0.75%. Furthermore, as opposed to other alternatives, the proposed technique satisfies the additional requirement of allowing evaluation using different TOL and microarchitectural configurations.
dc.format.extent11 p.
dc.language.isoeng
dc.publisherACM
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshComputer networks
dc.subject.lcshFault-tolerant computing
dc.subject.otherDynamic binary translation
dc.subject.otherHW/SW co-designed processors
dc.subject.otherSimulation
dc.subject.otherWarm-up methodology
dc.titleWarm-up simulation methodology for HW/SW co-designed processors
dc.typeConference report
dc.subject.lemacOrdinadors, Xarxes d'
dc.subject.lemacTolerància als errors (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1145/2544137.2544142
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://dl.acm.org/citation.cfm?id=2544142
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac13077590
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorBrankovic, A.; Stavrou, K.; Gibert, E.; Gonzalez, A.
local.citation.contributorInternational Symposium on Code Generation and Optimization
local.citation.pubplaceOrlando
local.citation.publicationNameProceedings of the 2014 CGO: the twelfth International Symposium on Code Generation and Optimization: February 15-19, 2014: Orlando, Florida
local.citation.startingPage284
local.citation.endingPage294


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