Show simple item record

dc.contributor.authorBrankovic, Aleksandar
dc.contributor.authorStavrou, K.
dc.contributor.authorGibert Codina, Enric
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationBrankovic, A. [et al.]. Warm-up simulation methodology for HW/SW co-designed processors. A: International Symposium on Code Generation and Optimization. "Proceedings of the 2014 CGO: the twelfth International Symposium on Code Generation and Optimization: February 15-19, 2014: Orlando, Florida". Orlando: ACM, 2014, p. 284-294.
dc.description.abstractEvaluation techniques in microprocessor design are mostly based on simulating selected application samples using a cycle-accurate simulator. In order to achieve accurate results, microarchitectural structures are warmed-up for a few million instructions prior to statistics collection. Unfortunately, this strategy cannot be applied to HW/SW co-designed processors, in which a Transparent Optimization software Layer (TOL) translates and optimizes code on-the-fly from a guest ISA to an internal host custom microarchitecture. We show that the warm-up period in this case needs to be 3-4 orders of magnitude longer than what is needed for traditional microprocessor designs because the TOL state needs to be warmed-up as well. In this paper, we propose a novel simulation technique for HW/SW co-designed processors based on adapting the optimization promotion thresholds using high level application statistics in order to find the best trade-off between accuracy and simulation cost. In particular, the proposed technique reduces the simulation cost by 65X with an average error of just 0.75%. Furthermore, as opposed to other alternatives, the proposed technique satisfies the additional requirement of allowing evaluation using different TOL and microarchitectural configurations.
dc.format.extent11 p.
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.subjectÀrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshComputer networks
dc.subject.lcshFault-tolerant computing
dc.subject.otherDynamic binary translation
dc.subject.otherHW/SW co-designed processors
dc.subject.otherWarm-up methodology
dc.titleWarm-up simulation methodology for HW/SW co-designed processors
dc.typeConference report
dc.subject.lemacOrdinadors, Xarxes d'
dc.subject.lemacTolerància als errors (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
dc.description.versionPostprint (published version)
local.citation.authorBrankovic, A.; Stavrou, K.; Gibert, E.; Gonzalez, A.
local.citation.contributorInternational Symposium on Code Generation and Optimization
local.citation.publicationNameProceedings of the 2014 CGO: the twelfth International Symposium on Code Generation and Optimization: February 15-19, 2014: Orlando, Florida

Files in this item


This item appears in the following Collection(s)

Show simple item record

Attribution-NonCommercial-NoDerivs 3.0 Spain
Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 3.0 Spain