Warm-up simulation methodology for HW/SW co-designed processors
Tipo de documentoTexto en actas de congreso
Fecha de publicación2014
Condiciones de accesoAcceso restringido por política de la editorial
Evaluation techniques in microprocessor design are mostly based on simulating selected application samples using a cycle-accurate simulator. In order to achieve accurate results, microarchitectural structures are warmed-up for a few million instructions prior to statistics collection. Unfortunately, this strategy cannot be applied to HW/SW co-designed processors, in which a Transparent Optimization software Layer (TOL) translates and optimizes code on-the-fly from a guest ISA to an internal host custom microarchitecture. We show that the warm-up period in this case needs to be 3-4 orders of magnitude longer than what is needed for traditional microprocessor designs because the TOL state needs to be warmed-up as well. In this paper, we propose a novel simulation technique for HW/SW co-designed processors based on adapting the optimization promotion thresholds using high level application statistics in order to find the best trade-off between accuracy and simulation cost. In particular, the proposed technique reduces the simulation cost by 65X with an average error of just 0.75%. Furthermore, as opposed to other alternatives, the proposed technique satisfies the additional requirement of allowing evaluation using different TOL and microarchitectural configurations.
CitaciónBrankovic, A. [et al.]. Warm-up simulation methodology for HW/SW co-designed processors. A: International Symposium on Code Generation and Optimization. "Proceedings of the 2014 CGO: the twelfth International Symposium on Code Generation and Optimization: February 15-19, 2014: Orlando, Florida". Orlando: ACM, 2014, p. 284-294.
Versión del editorhttp://dl.acm.org/citation.cfm?id=2544142
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