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dc.contributor.authorTorrents Lapuerta, Martí
dc.contributor.authorMartinez Morais, Raul
dc.contributor.authorMolina Clemente, Carlos
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-05-26T13:13:14Z
dc.date.created2014-06-01
dc.date.issued2014-06-01
dc.identifier.citationTorrents, M.; Martinez Morais, Raul; Molina, C. Network aware performance evaluation of prefetching techniques in CMPs. "Simulation modelling practice and theory", 01 Juny 2014, vol. 45, p. 1-17.
dc.identifier.issn1569-190X
dc.identifier.urihttp://hdl.handle.net/2117/23050
dc.description.abstractThis study focuses on the importance of quantifying the effect of prefetching on the interconnection network of a multiprocessor chip. This kind of microarchitectural effects are often quantified using simulators. However, if prefetching traffic in a CMP (Chip MultiProcessor) system is to be accurately evaluated, simulators should simulate not only the memory hierarchy module and the multicore system, but also the network-on-chip. Unfortunately, no open-source simulator is able to evaluate all these elements at the same time. This paper describes how to develop a prefetching module for the gem5 CMP simulator and how to integrate this into the Ruby memory system. Moreover, by using the infrastructure developed in this study, this paper shows the importance of taking the network effect in prefetching-related studies into account, in order for accurate results to be obtained: not doing so may lead to mistaken conclusions. For this purpose, we have carried out a detailed analysis of the behavior of three different prefetching engines, providing not only the typical statistics for instructions per cycle and the miss rate, but also specific network and prefetching statistics.
dc.format.extent17 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshComputer architecture
dc.subject.lcshMultiprocessors
dc.subject.otherCache coherence protocol
dc.subject.otherGem5
dc.subject.otherMulticore
dc.subject.otherNetwork-on-chip
dc.subject.otherPrefetching
dc.subject.otherSimulation infrastructure
dc.titleNetwork aware performance evaluation of prefetching techniques in CMPs
dc.typeArticle
dc.subject.lemacArquitectura d'ordinadors
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1016/j.simpat.2014.03.005
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://www.sciencedirect.com/science/article/pii/S1569190X14000434
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac14862225
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
local.citation.authorTorrents, M.; Martinez Morais, Raul; Molina, C.
local.citation.publicationNameSimulation modelling practice and theory
local.citation.volume45
local.citation.startingPage1
local.citation.endingPage17


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