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dc.contributor.authorKosmidis, Leonidas
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorQuiñones, Eduardo
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-04-07T14:27:14Z
dc.date.created2013
dc.date.issued2013
dc.identifier.citationKosmidis, L. [et al.]. Multi-level unified caches for probabilistically time analysable real-time systems. A: IEEE Real-Time Systems Symposium. "2013 IEEE 34th Real-Time Systems Symposium (RTSS 2013): 3-6 December 2013: Vancouver, Canada". Vancouver: IEEEXPLORE, 2013, p. 360-371.
dc.identifier.isbn978-147992007-5
dc.identifier.urihttp://hdl.handle.net/2117/22544
dc.description.abstractCaches are key resources in high-end processor architectures to increase performance. In fact, most high-performance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, cache hierarchies severely challenge the computation of tight worst-case execution time (WCET) estimates. On the one hand, the analysis of the timing behaviour of a single level of cache is already challenging, particularly for data accesses. On the other hand, unifying data and instructions in each level, makes the problem of cache analysis significantly more complex requiring tracking simultaneously data and instruction accesses to cache. In this paper we prove that multi-level cache hierarchies can be used in the context of Probabilistic Timing Analysis and tight WCET estimates can be obtained. Our detailed analysis (1) covers unified data and instruction caches, (2) covers different cache-write policies (write-through and write back), write allocation policies (write-allocate and non-write-allocate) and several inclusion mechanisms (inclusive, non-inclusive and exclusive caches), and (3) scales to an arbitrary number of cache levels. Our results show that the probabilistic WCET (pWCET) estimates provided by our analysis technique effectively benefit from having multi-level caches. For a two-level cache configuration and for EEMBC benchmarks, pWCET reductions are 55% on average (and up to 90%) with respect to a processor with a single level of cache.
dc.format.extent12 p.
dc.language.isoeng
dc.publisherIEEEXPLORE
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshReal-time data processing
dc.subject.lcshSystem design
dc.subject.otherMulti-level caches
dc.subject.otherProbabilistic timing analysis
dc.subject.otherWCET
dc.titleMulti-level unified caches for probabilistically time analysable real-time systems
dc.typeConference report
dc.subject.lemacDisseny de sistemes
dc.subject.lemacTemps real (Informàtica)
dc.identifier.doi10.1109/RTSS.2013.43
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6728890&tag=1
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac13676570
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC
dc.date.lift10000-01-01
local.citation.authorKosmidis, L.; Abella, J.; Quiñones, E.; Cazorla, F.
local.citation.contributorIEEE Real-Time Systems Symposium
local.citation.pubplaceVancouver
local.citation.publicationName2013 IEEE 34th Real-Time Systems Symposium (RTSS 2013): 3-6 December 2013: Vancouver, Canada
local.citation.startingPage360
local.citation.endingPage371


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Attribution-NonCommercial-NoDerivs 3.0 Spain
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