Show simple item record

dc.contributor.authorKosmidis, Leonidas
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorQuiñones, Eduardo
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-03-31T12:38:12Z
dc.date.created2013
dc.date.issued2013
dc.identifier.citationKosmidis, L. [et al.]. A cache design for probabilistically analysable real-time systems. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: Grenoble, France, March 18 - 22, 2013". Grenoble: 2013, p. 513-518.
dc.identifier.isbn978-398153700-0
dc.identifier.urihttp://hdl.handle.net/2117/22448
dc.description.abstractCaches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. Probabilistic Timing Analysis (PTA) has emerged as a solution to reduce the amount of information needed to provide tight WCET estimates, although it imposes new requirements on hardware design. At cache level, so far only fully-associative random-replacement caches have been proven to fulfill the needs of PTA, but they are expensive in size and energy. In this paper we propose a cache design that allows setassociative and direct-mapped caches to be analysed with PTA techniques. In particular we propose a novel parametric random placement suitable for PTA that is proven to have low hardware complexity and energy consumption while providing comparable performance to that of conventional modulo placement.
dc.format.extent6 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subject.lcshEmbedded computer systems
dc.subject.lcshFault-tolerant computing
dc.subject.otherAmount of information
dc.subject.otherCache access
dc.subject.otherHardware complexity
dc.subject.otherHardware design
dc.subject.otherRandom placement
dc.subject.otherSet-associative
dc.subject.otherTiming Analysis
dc.subject.otherWcet analysis
dc.titleA cache design for probabilistically analysable real-time systems
dc.typeConference report
dc.subject.lemacTolerància als errors (Informàtica)
dc.subject.lemacSistemes incrustats (Informàtica)
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://dl.acm.org/citation.cfm?id=2485288.2485416
dc.rights.accessRestricted access - publisher's policy
drac.iddocument12886143
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorKosmidis, L.; Abella, J.; Quiñones, E.; Cazorla, F.
upcommons.citation.contributorDesign, Automation and Test in Europe
upcommons.citation.pubplaceGrenoble
upcommons.citation.publishedtrue
upcommons.citation.publicationNameDesign, Automation and Test in Europe: Grenoble, France, March 18 - 22, 2013
upcommons.citation.startingPage513
upcommons.citation.endingPage518


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

Except where otherwise noted, content on this work is licensed under a Creative Commons license: Attribution-NonCommercial-NoDerivs 3.0 Spain