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dc.contributor.authorMauricio Ferré, Juan
dc.contributor.authorMoll Echeto, Francisco de Borja
dc.contributor.authorGómez Fernández, Sergio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2014-03-14T13:31:23Z
dc.date.created2014-02-01
dc.date.issued2014-02-01
dc.identifier.citationMauricio, J.; Moll, F.; Gomez, S. Measurements of process variability in 40-nm regular and nonregular layouts. "IEEE transactions on electron devices", 01 Febrer 2014, vol. 61, núm. 2, p. 365-371.
dc.identifier.issn0018-9383
dc.identifier.urihttp://hdl.handle.net/2117/22068
dc.description.abstractAs technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts are recommended to reduce variability with the cost of area overhead with respect to conventional layouts. The aim of this paper is to measure the impact of variability in two implementations of the same circuit in a commercial 40-nm technology: 1) a regular layout style and a compact and 2) nonregular layout. Experimental results show a 60% reduction in variability with a cost of 60% area overhead.
dc.format.extent7 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Components electrònics::Transistors
dc.subject.otherLithography distortion
dc.subject.otherVariability
dc.subject.otherFluctuations
dc.subject.otherMosfets
dc.titleMeasurements of process variability in 40-nm regular and nonregular layouts
dc.typeArticle
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/TED.2013.2294742
dc.description.peerreviewedPeer Reviewed
dc.subject.amsIntegrated circuits
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6691935
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac13607353
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/248538/EU/SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms/SYNAPTIC
dc.date.lift10000-01-01
local.citation.authorMauricio, J.; Moll, F.; Gomez, S.
local.citation.publicationNameIEEE transactions on electron devices
local.citation.volume61
local.citation.number2
local.citation.startingPage365
local.citation.endingPage371


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