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Measurements of process variability in 40-nm regular and nonregular layouts

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Measurements of Process Variability in 40-nm Regular and Nonregular Layouts (1,321Mb) (Restricted access)   Request copy 

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10.1109/TED.2013.2294742
 
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hdl:2117/22068

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Mauricio Ferré, Juan
Moll Echeto, Francisco de BorjaMés informacióMés informacióMés informació
Gómez Fernández, SergioMés informacióMés informacióMés informació
Document typeArticle
Defense date2014-02-01
Rights accessRestricted access - publisher's policy
Attribution-NonCommercial-NoDerivs 3.0 Spain
Except where otherwise noted, content on this work is licensed under a Creative Commons license : Attribution-NonCommercial-NoDerivs 3.0 Spain
ProjectSYNAPTIC - SYNthesis using Advanced Process Technology Integrated in regular Cells, IPs, architectures, and design platforms (EC-FP7-248538)
Abstract
As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts are recommended to reduce variability with the cost of area overhead with respect to conventional layouts. The aim of this paper is to measure the impact of variability in two implementations of the same circuit in a commercial 40-nm technology: 1) a regular layout style and a compact and 2) nonregular layout. Experimental results show a 60% reduction in variability with a cost of 60% area overhead.
CitationMauricio, J.; Moll, F.; Gomez, S. Measurements of process variability in 40-nm regular and nonregular layouts. "IEEE transactions on electron devices", 01 Febrer 2014, vol. 61, núm. 2, p. 365-371. 
URIhttp://hdl.handle.net/2117/22068
DOI10.1109/TED.2013.2294742
ISSN0018-9383
Publisher versionhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6691935
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  • HIPICS - High Performance Integrated Circuits and Systems - Articles de revista [92]
  • Departament d'Enginyeria Electrònica - Articles de revista [1.658]
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