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Títol: The design and control of dynamic memory networks
Autor: Fiol Mora, Miquel Àngel
Fàbrega Canudas, José
Yebra, José Luis A.
Altres autors/autores: Universitat Politècnica de Catalunya. Departament de Matemàtica Aplicada IV; Universitat Politècnica de Catalunya. COMBGRAF - Combinatòria, Teoria de Grafs i Aplicacions
Editorial: IEEE Press
Matèries: Àrees temàtiques de la UPC::Matemàtiques i estadística::Matemàtica discreta::Teoria de grafs
Graph theory
Computer systems
Dynamic memory
Interconnection network
Access time
Control
Grafs, Teoria de
Arquitectura de computadors
Classificació AMS::05 Combinatorics::05C Graph theory
Classificació AMS::68 Computer science::68M Computer system organization
Tipus de document: Conference report
Descripció: A dynamic memory is a storage medium constituted by an array of cells and an interconnection network between them. It is characterized by the constant circulation of the stored data. The concern is to design the interconnection network in order to have small access times and a simple control of the memory. Several interconnection schemes have been proosed in the literature. This paper presents a quite general model for such structures that greatly facilitates both the design and the control of the memory. It is shown that most known proposals of dynamic memory interconnection networks are particular instances of the model and that it leads to some new ones.
A quite general model for dynamic memory networks is proposed that greatly facilitates both the design and the control of the memory. It is shown that most known proposals of dynamic memory interconnection networks are particular instances of the model and that it leads to some novel networks. The discussion covers Cayley diagrams, de Bruijn digraphs, the memory of A.V. Aho and J.D. Ullman (1974), odd-sized memories, J. Lenfant's memories (1977), an optimal-size memory, and vectorial dynamic memories
Peer reviewed
Altres identificadors i accés: Fiol, M.A.; Fabrega, J.; Yebra, J.L.A. "The design and control of dynamic memory networks". A: IEEE International Symposium on Circuits and Systems, 1988, vol. 1, p. 175-179.
http://hdl.handle.net/2117/2203
Disponible al dipòsit:E-prints UPC
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