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Impact of finfet and III-V/Ge technology on logic and memory cell behavior

dc.contributor.authorAmat Bertran, Esteve
dc.contributor.authorCalomarde Palomino, Antonio
dc.contributor.authorGarcía Almudéver, Carmen
dc.contributor.authorAymerich Capdevila, Nivard
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2014-03-06T19:20:47Z
dc.date.created2013-11-20
dc.date.issued2013-11-20
dc.identifier.citationAmat, E. [et al.]. Impact of finfet and III-V/Ge technology on logic and memory cell behavior. "IEEE transactions on device and materials reliability", 20 Novembre 2013, vol. 14, núm. 1, p. 1-15.
dc.identifier.issn1530-4388
dc.identifier.urihttp://hdl.handle.net/2117/21907
dc.description.abstractIn this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios (variability and soft errors). FinFET-based circuits show the highest robustness against variability and soft error environments.
dc.format.extent15 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshIntegrated circuits
dc.subject.otherDRAM
dc.subject.otherIII–V semiconductor materials
dc.subject.otherIntegrated circuit reliability
dc.subject.otherRing oscillators
dc.titleImpact of finfet and III-V/Ge technology on logic and memory cell behavior
dc.typeArticle
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/TDMR.2013.2291410
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6670777
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac13031806
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/TRAMS
dc.date.lift10000-01-01
local.citation.authorAmat, E.; Calomarde, A.; Garcia, C.; Aymerich, N.; Canal, R.; Rubio, J.A.
local.citation.publicationNameIEEE transactions on device and materials reliability
local.citation.volume14
local.citation.number1
local.citation.startingPage1
local.citation.endingPage15


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