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dc.contributor.authorSlijepcevic, Mladen
dc.contributor.authorKosmidis, Leonidas
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorQuiñones, Eduardo
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationSlijepcevic, M. [et al.]. DTM: degraded test mode for fault-aware probabilistic timing analysis. A: Euromicro Conference on Real-Time Systems. "Proceedings of the 25th Euromicro Conference on Real-Time Systems: ECRTS 2013: Paris, France: 9-12 July 2013". Paris: Institute of Electrical and Electronics Engineers (IEEE), 2013, p. 237-248.
dc.description.abstractExisting timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current Critical Real-Time Embedded Systems (CRTES), the use of high-performance features and smaller transistors in current and future hardware becomes a must. The use of smaller transistors helps providing more performance while maintaining low energy budgets, however, hardware fault rates increase noticeably, affecting the temporal behaviour of the system in general, and WCET in particular. In this paper, we reconcile these two emergent needs of CRTES, namely, tight (and trustworthy) WCET estimates and the use of hardware implemented with smaller transistors. To that end we propose the Degraded Test Mode (DTM) that, in combination with fault-tolerant hardware designs and probabilistic timing analysis techniques, (i) enables the computation of tight and trustworthy WCET estimates in the presence of faults, (ii) provides graceful average and worst-case performance degradation due to faults, and (iii) requires modifications neither in WCET analysis tools nor in applications. Our results show that DTM allows accounting for the effect of faults at analysis time with low impact in WCET estimates and negligible hardware modifications.
dc.format.extent12 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.subjectÀrees temàtiques de la UPC::Informàtica::Hardware
dc.subject.lcshEmbedded computer systems
dc.subject.lcshFault-tolerant computing
dc.subject.otherProbabilistic timing analysis
dc.titleDTM: degraded test mode for fault-aware probabilistic timing analysis
dc.typeConference report
dc.subject.lemacSistemes incrustats (Informàtica)
dc.subject.lemacTolerància als errors (Informàtica)
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/287759/EU/High Performance and Embedded Architecture and Compilation/HIPEAC
upcommons.citation.authorSlijepcevic, M.; Kosmidis, L.; Abella, J.; Quiñones, E.; Cazorla, F.
upcommons.citation.contributorEuromicro Conference on Real-Time Systems
upcommons.citation.publicationNameProceedings of the 25th Euromicro Conference on Real-Time Systems: ECRTS 2013: Paris, France: 9-12 July 2013

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