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dc.contributor.authorAymerich Capdevila, Nivard
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.identifier.citationAymerich, N.; Rubio, J.A. Extending the fundamental error bounds for asymmetric error reliable computation. A: IEEE/ACM International Symposium on Nanoscale Architectures. "Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH): 15–17 July 2013: New York City, USA". New York: IEEE Industrial Electronics Society, 2013, p. 106-109.
dc.description.abstractFuture computing systems based on new emerging nanotechnologies will have to rely on very high failure rate devices. Therefore, the study of fault-tolerant architectures is of great interest today. One of the most challenging problems of this research area consists in finding the fundamental error bounds beyond which reliable computation is not possible. In the literature we can find the exact error threshold for circuits built out of noisy NAND gates under the von Neumann's probabilistic computing framework. In this paper we extend this result for asymmetric error designs and demonstrate that it is possible to compute reliably with 2-input noisy NAND gates beyond the well known error bound: ∈* = (3 - √7)/4.
dc.format.extent4 p.
dc.publisherIEEE Industrial Electronics Society
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshFault tolerance (Engineering)
dc.subject.lcshIntegrated circuits
dc.subject.otherNano architectures
dc.subject.otherFault tolerance
dc.subject.otherFault tolerant systems
dc.subject.otherLogic gates
dc.subject.otherNoise measurement
dc.subject.otherReliability theory
dc.titleExtending the fundamental error bounds for asymmetric error reliable computation
dc.typeConference report
dc.subject.lemacTolerància als errors (Enginyeria
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
dc.description.versionPostprint (published version)
local.citation.authorAymerich, N.; Rubio, J.A.
local.citation.contributorIEEE/ACM International Symposium on Nanoscale Architectures
local.citation.pubplaceNew York
local.citation.publicationNameProceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH): 15–17 July 2013: New York City, USA

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