Task sampling: computer architecture simulation in the many-core era
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Document typeConference report
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Chip Multi-Processors (CMPs) are evolving towards ever increasing core counts. Task-based programming models are a promising candidate for exploiting the parallelism offered by these machines. Simulation, the prevailing design methodology in computer architecture, is prohibitively time consuming, when it comes to CMPs featuring 1000s of cores. Sampled simulation is a standard technique for reducing simulation time for single-threaded architectures. Recently, these techniques have been extended to allow for simulation of multi-threaded systems. However, they have not been assessed for dynamically scheduled multi-threaded programs. In this work we use the OmpSs programming model . OmpSs, an extension of OpenMP, allows to declare code blocks as tasks and to specify data consumed and produced by each task. The runtime environment executes tasks, potentially out of program order, on available cores, similar to the out-oforder execution in a superscalar processor.
CitationGrass, T. Task sampling: computer architecture simulation in the many-core era. A: International Conference on Parallel Architectures and Compilation Techniques. "Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, Edinburgh, United Kingdom, September 7-11, 2013". Edinburgh: 2013, p. 405.
|Task sampling c ... n in the many core era.pdf||Task sampling computer architecture simulation in the many core era||74,95Kb||Restricted access|