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Fast self-reconfigurable embedded system on Spartan-3
dc.contributor.author | Camós Andreu, Carles |
dc.contributor.author | Fons, Mariano |
dc.contributor.author | Fons, Francesc |
dc.contributor.author | López García, Mariano |
dc.contributor.author | Ramos Lara, Rafael Ramón |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2013-12-17T09:09:33Z |
dc.date.available | 2013-12-17T09:09:33Z |
dc.date.created | 2013-02 |
dc.date.issued | 2013-02 |
dc.identifier.citation | Cantó, E. [et al.]. Fast self-reconfigurable embedded system on Spartan-3. "Journal of universal computer science", Febrer 2013, vol. 19, núm. 3, p. 301-324. |
dc.identifier.issn | 0948-695X |
dc.identifier.uri | http://hdl.handle.net/2117/21015 |
dc.description.abstract | Many image-processing algorithms require several stages to be processed that cannot be resolved by embedded microprocessors in a reasonable time, due to their high-computational cost. A set of dedicated coprocessors can accelerate the resolution of these algorithms, alt hough the main drawback is the area needed for their implementation. The main advantage of a reconfigurable system is that several coprocessors designed to perform different operations can be mapped on the same area in a time-multiplexed way. This work presents the architecture of an embedded system composed of a microprocessor and a run-time reconfigurable coprocessor, mapped on Spartan-3, the low-cost family of Xilinx FPGAs. Designing reconfigurable systems on Spartan-3 requires much design effort, since unlike higher cost families of Xilinx FPGAs, this device does not officially support partial reconfiguration. In order to overcome this drawback, the paper also describes the main steps used in the design flow to obtain a successful design. The main goal of the presented architecture is to reduce the coprocessor reconfiguration time, as well as accelerate image-processing algorithms. The experimental results demonstrate significant improvement in both objectives. The reconfiguration rate nearly achieves 320 Mb/s which is far superior to th e previous related works. |
dc.format.extent | 24 p. |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject.lcsh | Field programmable gate arrays |
dc.subject.lcsh | Embedded computer systems |
dc.subject.other | FPGA |
dc.subject.other | Spartan-3 |
dc.subject.other | partial reconfiguration |
dc.subject.other | embedded system |
dc.subject.other | image-processing |
dc.subject.other | reconfigurable coprocessor |
dc.subject.other | hardware accelerator |
dc.title | Fast self-reconfigurable embedded system on Spartan-3 |
dc.type | Article |
dc.subject.lemac | Circuits integrats digitals |
dc.subject.lemac | Microprocessadors |
dc.contributor.group | Universitat Politècnica de Catalunya. SARTI - Centre de Desenvolupament Tecnològic de Sistemes d'Adquisició Remota i Tractament de la Informació |
dc.identifier.doi | 10.3217/jucs-019-03-0301 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://www.jucs.org/jucs_19_3/fast_self_reconfigurable_embedded/jucs_19_03_0301_0324_canto.pdf |
dc.rights.access | Open Access |
local.identifier.drac | 12916736 |
dc.description.version | Postprint (published version) |
local.citation.author | Cantó, E.; Fons, M.; Fons, F.; Lopez, M.; Ramos, R. |
local.citation.publicationName | Journal of universal computer science |
local.citation.volume | 19 |
local.citation.number | 3 |
local.citation.startingPage | 301 |
local.citation.endingPage | 324 |
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