Many image-processing algorithms require several stages to be processed that cannot
be resolved by embedded microprocessors in a reasonable time, due to their high-computational
cost. A set of dedicated coprocessors can accelerate the resolution of these algorithms, alt
hough
the main drawback is the area needed for their implementation. The main advantage of a
reconfigurable system is that several coprocessors designed to perform different operations can
be mapped on the same area in a time-multiplexed
way. This work presents the architecture of
an embedded system composed of a microprocessor and a run-time reconfigurable coprocessor,
mapped on Spartan-3, the low-cost family of Xilinx FPGAs. Designing reconfigurable systems
on Spartan-3 requires much design effort, since unlike higher cost families of Xilinx FPGAs,
this device does not officially support partial reconfiguration. In order to overcome this
drawback, the paper also describes the main steps used in the design flow to obtain a successful
design. The main goal of the presented architecture is to reduce the coprocessor reconfiguration
time, as well as accelerate image-processing algorithms. The experimental results demonstrate
significant improvement in both objectives. The reconfiguration rate nearly achieves 320 Mb/s
which is far superior to th
e previous related works.
