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dc.contributor.authorCortadella, Jordi
dc.contributor.authorSan Pedro Martín, Javier de
dc.contributor.authorNikitin, Nikita
dc.contributor.authorPetit Silvestre, Jordi
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Llenguatges i Sistemes Informàtics
dc.date.accessioned2013-11-11T16:08:24Z
dc.date.available2013-11-11T16:08:24Z
dc.date.created2013
dc.date.issued2013
dc.identifier.citationCortadella, J. [et al.]. Physical-aware system-level design for tiled hierarchical chip multiprocessors. A: International Symposium on Physical Design. "ISPD '13: Proceedings of the 2013 ACM International Symposium on Physical Design: March 24-27, 2013, Stateline, Nevada". Stateline, Nevada: ACM Press. Association for Computing Machinery, 2013, p. 3-10.
dc.identifier.isbn978-1-4503-1867-9
dc.identifier.urihttp://hdl.handle.net/2117/20573
dc.description.abstractTiled hierarchical architectures for Chip Multiprocessors (CMPs) represent a rapid way of building scalable and power-e fficient many-core computing systems. At the early stages of the design of a CMP, physical parameters are often ignored and postponed for later design stages. In this work, the importance of physical-aware system-level exploration is investigated, and a strategy for deriving chip floorplans is described. Additionally, wire planning of the on-chip interconnect is performed, as its topology and organization aff ect the physical layout of the system. Traditional algorithms for floorplanning and wire planning are customized to include physical constraints speci c for tiled hierarchical architectures. Over-the-cell routing is used as one of the major area savings strategy. The combination of architectural exploration and physical planning is studied with an example and the impact of the physical aspects on the selection of architectural parameters is evaluated.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherACM Press. Association for Computing Machinery
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors
dc.subject.otherNetwork-on-chip
dc.subject.otherFloorplanning
dc.subject.otherWire planning
dc.subject.otherChip multiprocessor
dc.titlePhysical-aware system-level design for tiled hierarchical chip multiprocessors
dc.typeConference report
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1145/2451916.2451920
dc.rights.accessOpen Access
drac.iddocument12464416
dc.description.versionPostprint (author’s final draft)
upcommons.citation.authorCortadella, J.; De San Pedro, J.; Nikitin, N.; Petit, J.
upcommons.citation.contributorInternational Symposium on Physical Design
upcommons.citation.pubplaceStateline, Nevada
upcommons.citation.publishedtrue
upcommons.citation.publicationNameISPD '13: Proceedings of the 2013 ACM International Symposium on Physical Design: March 24-27, 2013, Stateline, Nevada
upcommons.citation.startingPage3
upcommons.citation.endingPage10


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