Show simple item record

dc.contributor.authorLorente, Vicente
dc.contributor.authorValero, Alejandro
dc.contributor.authorSahuquillo, Julio
dc.contributor.authorPetit, Salvador
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorLópez, Pedro
dc.contributor.authorDuato, José
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationLorente, V. [et al.]. Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. A: Design, Automation and Test in Europe. "Design, Automation & Test in Europe: Grenoble, France, March 18-22, 2013: proceedings". Grenoble: 2013, p. 83-88.
dc.description.abstractLow-power modes in modern microprocessors rely on low frequencies and low voltages to reduce the energy budget. Nevertheless, manufacturing induced parameter variations can make SRAM cells unreliable producing hard errors at supply voltages below Vccmin. Recent proposals provide a rather low fault-coverage due to the fault coverage/overhead trade-off. We propose a new fault- tolerant L1 cache, which combines SRAM and eDRAM cells in L1 data caches to provide 100% SRAM hard-error fault coverage. Results show that, compared to a conventional cache and assuming 50% failure probability at low-power mode, leakage and dynamic energy savings are by 85% and 62%, respectively, with a minimal impact on performance.
dc.format.extent6 p.
dc.subjectÀrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshInformation storage and retrieval systems
dc.subject.lcshCache memory
dc.titleCombining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes
dc.typeConference report
dc.subject.lemacInformació -- Sistemes d'emmagatzematge i recuperació
dc.subject.lemacMemòria ràpida de treball (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/248789/EU/TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS/TRAMS
upcommons.citation.authorLorente, V.; Valero, A.; Sahuquillo, J.; Petit, S.; Canal, R.; López, P.; Duato, J.
upcommons.citation.contributorDesign, Automation and Test in Europe
upcommons.citation.publicationNameDesign, Automation & Test in Europe: Grenoble, France, March 18-22, 2013: proceedings

Files in this item


This item appears in the following Collection(s)

Show simple item record

All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder