BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing
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Document typeConference report
Defense date2013
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
All rights reserved. This work is protected by the corresponding intellectual and industrial
property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public
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Abstract
Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done at different stages of the fabrication process. In this context, this work proposes a simple pre-bond GIST architecture to improve the detection of hard and weak defects
Description
built-in self test integrated circuit testing three-dimensional integrated circuits
CitationArumi, D.; Rodriguez, R.; Figueras, J. BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing. A: IEEE European Test Symposium. "Proceedings of 18th IEEE European Test Symposium". Avignon: Institute of Electrical and Electronics Engineers (IEEE), 2013.
ISBN978-1-4673-6377-8
Collections
- QINE - Disseny de Baix Consum, Test, Verificació i Tolerància a Fallades - Ponències/Comunicacions de congressos [60]
- QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat - Ponències/Comunicacions de congressos [78]
- Departament d'Enginyeria Electrònica - Ponències/Comunicacions de congressos [1.728]
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