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dc.contributor.authorNikitin, Nikita
dc.contributor.authorSan Pedro Martín, Javier de
dc.contributor.authorCortadella, Jordi
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament de Llenguatges i Sistemes Informàtics
dc.date.accessioned2013-10-22T12:34:01Z
dc.date.created2013
dc.date.issued2013
dc.identifier.citationNikitin, N.; De San Pedro, J.; Cortadella, J. Architectural exploration of large-scale hierarchical chip multiprocessors. "IEEE transactions on computer-aided design of integrated circuits and systems", Octubre 2013, vol. 32, núm. 10, p. 1569-1582.
dc.identifier.issn0278-0070
dc.identifier.urihttp://hdl.handle.net/2117/20442
dc.description.abstractThe continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more hierarchical structures to better exploit locality. To efficiently discover promising architectures within the rapidly growing search space, exhaustive exploration is replaced with tools that implement intelligent search strategies. Moreover, faster analytical models are preferred to costly simulations for estimating the performance and power of CMP architectures. The memory traffic generated by CMP cores has a cyclic dependency with the latency of the memory subsystem, which critically affects the overall system performance. Based on this observation, a novel scalable analytical method is proposed to estimate the performance of highly parallel CMPs (hundreds or thousands of cores) with hierarchical interconnect networks. The method can use customizable probabilistic models and solves the cyclic dependencies between traffic and latency by using a fixed-point strategy. By using the analytical model as a performance and power estimator, an efficient metaheuristic-based search is proposed for the exploration of large design spaces. The proposed techniques are shown to be very accurate and a promising strategy when compared to the results obtained by simulation.
dc.format.extent14 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshNanoelectronics
dc.subject.otherAnalytical modeling chip multiprocessing design space exploration metaheuristics numerical methods
dc.titleArchitectural exploration of large-scale hierarchical chip multiprocessors
dc.typeArticle
dc.subject.lemacNanoelectrònica
dc.contributor.groupUniversitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals
dc.identifier.doi10.1109/TCAD.2013.2272539
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/6600876
dc.rights.accessRestricted access - publisher's policy
drac.iddocument12827384
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorNikitin, N.; De San Pedro, J.; Cortadella, J.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIEEE transactions on computer-aided design of integrated circuits and systems
upcommons.citation.volume32
upcommons.citation.number10
upcommons.citation.startingPage1569
upcommons.citation.endingPage1582


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